公开(公告)号：US06462994B2

公开(公告)日：2002-10-08

申请号：US09929930

申请日：2001-08-15

申请人： Jae Hoon Kim

发明人： Jae Hoon Kim

IPC分类号： G11C700

CPC分类号： G11C29/804

摘要： A semiconductor memory device includes an address buffer for receiving an external address. A row decoder and a column decoder respectively decode a row address and a column address, and respectively generate a word line selecting signal and a bit line selecting signal. A memory cell array has cells. Each cell is activated by a selection of a word line and,a bit line. A redundancy logic cell replaces defect cells in the memory cell array. Latches store defect cell addresses corresponding to the defect cells in the memory cell array. Comparators output repair signals when an address stored in the latches corresponds to the external address. A redundancy controller generates a control signal to intercept signals corresponding to the defect cells in response to a repair signal, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells.

摘要翻译： 半导体存储器件包括用于接收外部地址的地址缓冲器。 行解码器和列解码器分别解码行地址和列地址，并分别产生字线选择信号和位线选择信号。 存储单元阵列具有单元。 每个单元格通过字线和位线的选择来激活。 冗余逻辑单元代替存储单元阵列中的缺陷单元。 锁存器存储对应于存储单元阵列中的缺陷单元的缺陷单元地址。 当存储在锁存器中的地址对应于外部地址时，比较器输出修复信号。 冗余控制器响应于修复信号产生控制信号以截取对应于缺陷单元的信号，并产生另一个控制信号，以使能冗余逻辑单元的读/写操作代替缺陷单元。

公开(公告)号：US06376903B1

公开(公告)日：2002-04-23

申请号：US09557799

申请日：2000-04-25

申请人： Jae Hoon Kim

发明人： Jae Hoon Kim

IPC分类号： H01L2302

CPC分类号： H01L24/49 ,  H01L23/4951 ,  H01L23/49537 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package includes a semiconductor chip having a plurality of contact pads, a plurality of first leads, a plurality of second leads and a housing. Each of the first leads includes an inner lead portion which is electrically coupled to an associated contact pad on the semiconductor chip, and an outer lead portion which extends from the inner lead portion and is exposed outside of the package. The second leads are disposed in an overlapping relationship with the first leads and are electrically insulated from the first leads. The second leads each include an inner lead portion electrically coupled to an associated contact pad on the semiconductor chip and an outer lead portion which extends from the inner lead portion and is exposed outside the package. The housing encapsulates the semiconductor chip and the inner lead portions of the plurality of first and second leads.

摘要翻译： 半导体芯片封装包括具有多个接触焊盘，多个第一引线，多个第二引线和外壳的半导体芯片。 每个第一引线包括电连接到半导体芯片上的相关接触焊盘的内引线部分和从内引线部分延伸并暴露在封装外部的外引线部分。 第二引线以与第一引线重叠的关系设置，并与第一引线电绝缘。 第二引线各自包括电连接到半导体芯片上的相关接触焊盘的内引线部分和从内引线部分延伸并暴露在封装外部的外引线部分。 壳体封装了多个第一和第二引线的半导体芯片和内部引线部分。