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    SYSTEMS FOR ESTIMATING BIT ERROR RATE (BER) OF ENCODED DATA USING NEURAL NETWORKS
    121.
    发明申请
    SYSTEMS FOR ESTIMATING BIT ERROR RATE (BER) OF ENCODED DATA USING NEURAL NETWORKS 有权

    公开(公告)号：US20230115877A1

    公开(公告)日：2023-04-13

    申请号：US17496703

    申请日：2021-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G06F11/10 ,  G06N3/04

    Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks, to estimate a bit error rate (BER) of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous to estimate a BER of encoded data, e.g., to facilitate decoding of the encoded data. In this manner, neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by comparing an estimated BER to a threshold (e.g., a threshold BER level) prior to decoding of the encoded data. For example, an additional NN activation indication may be provided, e.g., to indicate that the encoded data may be decoded or to indicate that error present in the encoded data is to be reduced.

    Systems for error reduction of encoded data using neural networks
    123.
    发明授权
    Systems for error reduction of encoded data using neural networks 有权

    公开(公告)号：US11563449B2

    公开(公告)日：2023-01-24

    申请号：US17302228

    申请日：2021-04-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: H03M13/37 ,  G06F7/544 ,  G06N3/08

    Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.

    Computational storage and networked based system
    124.
    发明授权
    Computational storage and networked based system 有权

    公开(公告)号：US11550500B2

    公开(公告)日：2023-01-10

    申请号：US16832737

    申请日：2020-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

    IPC: G06F3/06

    Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

    System on a Chip with Deep Learning Accelerator and Random Access Memory
    125.
    发明申请
    System on a Chip with Deep Learning Accelerator and Random Access Memory 有权

    公开(公告)号：US20230004804A1

    公开(公告)日：2023-01-05

    申请号：US17940343

    申请日：2022-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N5/04

    Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. An integrated circuit may be configured with: a central processing unit, a deep learning accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an artificial neural network executable by the deep learning accelerator and second instructions of an application executable by the central processing unit; one or connections among the random access memory, the deep learning accelerator and the central processing unit; and an input/output interface to an external peripheral bus. While the deep learning accelerator is executing the first instructions to convert sensor data according to the artificial neural network to inference results, the central processing unit may execute the application that uses inference results from the artificial neural network.

    MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS
    126.
    发明申请
    MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS 有权

    公开(公告)号：US20220398190A1

    公开(公告)日：2022-12-15

    申请号：US17888748

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

    IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864

    Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

    Wireless devices and systems including examples of compensating power amplifier noise
    127.
    发明授权
    Wireless devices and systems including examples of compensating power amplifier noise 有权

    公开(公告)号：US11528043B2

    公开(公告)日：2022-12-13

    申请号：US17162992

    申请日：2021-01-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Jeremy Chritz ,  Jaime Cummins ,  Tamara Schmitz

    IPC: H04B1/04 ,  H04L1/00 ,  H03M13/15 ,  H04L5/14 ,  H04L5/00 ,  H04B1/12 ,  H04B1/525

    Abstract: Examples described herein include methods, devices, and systems which may compensate input data for non-linear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a coefficient calculator. The coefficient calculator may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to a coefficient calculator. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.

    System on a chip with deep learning accelerator and random access memory
    129.
    发明授权
    System on a chip with deep learning accelerator and random access memory 有权

    公开(公告)号：US11461651B2

    公开(公告)日：2022-10-04

    申请号：US16845002

    申请日：2020-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N5/04

    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured with: a Central Processing Unit, a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of an application executable by the Central Processing Unit; one or connections among the random access memory, the Deep Learning Accelerator and the Central Processing Unit; and an input/output interface to an external peripheral bus. While the Deep Learning Accelerator is executing the first instructions to convert sensor data according to the Artificial Neural Network to inference results, the Central Processing Unit may execute the application that uses inference results from the Artificial Neural Network.

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