公开(公告)号：US20250167811A1

公开(公告)日：2025-05-22

申请号：US19028790

申请日：2025-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins

IPC: H03M13/37 ,  G06F7/544 ,  G06N3/08

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.

公开(公告)号：US12143266B2

公开(公告)日：2024-11-12

申请号：US17321283

申请日：2021-05-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04L41/0813 ,  H04L41/0806 ,  H04L41/0823 ,  H04L41/0859 ,  H04L67/12 ,  H04W76/28

Abstract: Examples described herein include methods, devices, and systems which may implement different processing stages for wireless communication in processing units. Such data processing may include a source data processing stage, a baseband processing stage, a digital front-end processing stage, and a radio frequency (RF) processing stage. Data may be received from a sensor of device and then processed in the stages to generate output data for transmission. Processing the data in the various stages may occur during an active time period of a discontinuous operating mode. During the active time period, a reconfigurable hardware platform may allocate all or a portion of the processing units to implement the processing stages. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11973513B2

公开(公告)日：2024-04-30

申请号：US17302226

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins

IPC: G06F11/00 ,  G06N3/049 ,  G06N3/08 ,  H03M13/01 ,  H03M13/11 ,  H03M13/13

CPC classification number: H03M13/01 ,  G06N3/049 ,  G06N3/08 ,  H03M13/1105 ,  H03M13/1148 ,  H03M13/13

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate message probability compute data based on encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate message probability compute data for a message probability compute (MPC) decoder. In this manner, neural networks or recurrent neural networks described herein may be used to implement aspects of error correction coding (ECC) decoders, e.g., an MPC decoder that iteratively decodes encoded data.

公开(公告)号：US20240125851A1

公开(公告)日：2024-04-18

申请号：US18047386

申请日：2022-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

CPC classification number: G01R31/31907 ,  G01R31/318594 ,  G01R31/318597

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

公开(公告)号：US11942135B2

公开(公告)日：2024-03-26

申请号：US17729830

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G11C11/34 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06N3/063 ,  H04N23/69 ,  H04N23/80

CPC classification number: G11C11/34 ,  G06F9/30007 ,  G06F9/3893 ,  G06F9/5027 ,  G06N3/063 ,  H04N23/69 ,  H04N23/80

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US11887647B2

公开(公告)日：2024-01-30

申请号：US16844993

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G06F9/38 ,  G11C11/34 ,  G06F9/30 ,  G06N3/063 ,  G06F9/50 ,  G06N3/10 ,  G06F17/16

CPC classification number: G11C11/34 ,  G06F9/30007 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/5027 ,  G06F17/16 ,  G06N3/063 ,  G06N3/10

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to a direct memory access controller. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the direct memory access controller may concurrently load next input into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US11695503B2

公开(公告)日：2023-07-04

申请号：US17394601

申请日：2021-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Jeremy Chritz ,  Tamara Schmitz

IPC: H04K1/10 ,  H04L27/28 ,  H04L1/00 ,  H04L27/00 ,  H04L27/26 ,  H04B1/04

CPC classification number: H04L1/0045 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/0008 ,  H04L27/2628 ,  H04L27/2646 ,  H04B2001/0408 ,  H04L27/26414 ,  H04L27/26416

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. The processing mode selection may include a single processing mode, a multi-processing mode, or a full processing mode. The processing mode selection may be associated with an aspect of a wireless protocol. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US20230163788A1

公开(公告)日：2023-05-25

申请号：US18158332

申请日：2023-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins

IPC: H03M13/37 ,  G06F7/544

CPC classification number: H03M13/37 ,  G06F7/5443 ,  G06N3/08

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.

公开(公告)号：US20230161512A1

公开(公告)日：2023-05-25

申请号：US18152063

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0658 ,  G06F3/061 ,  G06F3/0683 ,  G06F3/067

Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

公开(公告)号：US11575548B2

公开(公告)日：2023-02-07

申请号：US16983797

申请日：2020-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jeremy Chritz ,  Jaime Cummins ,  Tamara Schmitz

IPC: H04L25/08 ,  H04B17/21 ,  H04B17/345 ,  H04B1/10 ,  H04B1/12 ,  H04B1/525 ,  H04L27/26 ,  H04L5/00 ,  H04L5/14 ,  H04L25/02 ,  H04L25/03 ,  H04B7/04

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.