公开(公告)号：US06721224B2

公开(公告)日：2004-04-13

申请号：US10228530

申请日：2002-08-26

Applicant: Steve S. Eaton ,  Michael Murray ,  Li-Chun Li

Inventor： Steve S. Eaton ,  Michael Murray ,  Li-Chun Li

IPC: G11C700

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C2211/4061

Abstract: A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

Abstract translation: 只有在读取操作结束时或存储器被禁用但应保留数据处于禁用状态时，存储器才会执行隐藏刷新。 当存储器处于使能状态时，刷新不会在读取以外的任何操作结束时执行。 这是为了确保任何存储器访问命令的执行不会被刷新延迟，只要用户遵循特定的时序规则。 还提供了其他实施例。

公开(公告)号：US5949722A

公开(公告)日：1999-09-07

申请号：US62175

申请日：1998-04-16

Applicant: Lawrence Liu ,  Li-Chun Li ,  Michael Murray

Inventor： Lawrence Liu ,  Li-Chun Li ,  Michael Murray

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C7/1048 ,  G11C11/4096 ,  G11C7/1051

Abstract: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.

Abstract translation: 在MOS存储器件中使用的输入/输出偏置电路对无意的电源变化不敏感。 被编程为给定状态的存储器单元具有连接到第一节点的终端。 第一个MOS开关，常开，连接在第一个节点和一个接地端子之间。 常闭的偏置电路和第二MOS开关连接在电源端子和第一节点之间。 第一节点连接到读出放大器的两个输入端之一，第二输入端连接到读出放大器使能/禁止信号。 在选择存储单元时，第一开关被接通并且第二开关在第一时间段被关闭。 在此期间，偏置电路和第一开关相互作用以将第一节点偏置到等于低于电源电压的一个阈值电压的电位。 在第一时间段之后的第二时间段内，两个开关1和2都断开。 在此期间，偏置电路与存储器单元交互以将第一节点偏置到与存储器单元的状态相对应的电位。 而且在第二时段期间，读出放大器能够通过感测第一节点上的电位来检测存储器单元的状态。

公开(公告)号：US5812474A

公开(公告)日：1998-09-22

申请号：US733858

申请日：1996-10-18

Applicant: Lawrence Liu ,  Li-Chun Li ,  Michael Murray

Inventor： Lawrence Liu ,  Li-Chun Li ,  Michael Murray

IPC: G11C7/10 ,  G11C7/02

CPC classification number: G11C7/1048

Abstract: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.