公开(公告)号：US5768200A

公开(公告)日：1998-06-16

申请号：US760121

申请日：1996-12-03

申请人： Lawrence Liu ,  Michael Murray ,  Li-Chun Li

发明人： Lawrence Liu ,  Michael Murray ,  Li-Chun Li

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/065

摘要： A sense amplifier charging circuit can work with different power supply voltages (EVCC). When EVCC is high, a signal generated from EVCC disables some of the charging transistors to reduce the circuit noise. When EVCC is low, the signal generated from EVCC enables the transistors thus increasing the circuit speed.

摘要翻译： 读出放大器充电电路可以工作在不同的电源电压（EVCC）。 当EVCC为高电平时，从EVCC产生的信号禁止某些充电晶体管降低电路噪声。 当EVCC为低电平时，从EVCC产生的信号使得晶体管能够提高电路速度。

公开(公告)号：US5767737A

公开(公告)日：1998-06-16

申请号：US695058

申请日：1996-08-09

申请人： Lawrence Liu ,  Michael Murray ,  Li-Chun Li

发明人： Lawrence Liu ,  Michael Murray ,  Li-Chun Li

IPC分类号： G11C7/06 ,  G05F1/10

CPC分类号： G11C7/06

摘要： A dynamic random access memory generates an internal power supply voltage IVCC. IVCC is lower in magnitude than the external power supply voltage EVCC. During a read operation, the sense amplifiers are powered from EVCC while the bit lines charge to their output levels. Then the sense amplifiers stop being powered from EVCC and begin being powered from IVCC to maintain the bit lines at their output levels. A timer defines the time that the sense amplifiers are powered from EVCC. This time depends inversely on EVCC. The timer includes a transistor connected between EVCC and an input of the inverter. The time that the sense amplifiers are powered from EVCC is defined by the time that the input of the inverter charges to the trip point of the inverter.

摘要翻译： 动态随机存取存储器产生内部电源电压IVCC。 IVCC的幅度小于外部电源电压EVCC。 在读操作期间，读出放大器由EVCC供电，同时位线充电到其输出电平。 然后，感测放大器停止从EVCC供电，并开始从IVCC供电，以将位线保持在其输出电平。 定时器定义了感测放大器从EVCC供电的时间。 这一次与EVCC相反。 定时器包括连接在EVCC和反相器的输入端之间的晶体管。 读出放大器由EVCC供电的时间由变频器的输入充电到变频器的跳变点的时间决定。

公开(公告)号：US5949722A

公开(公告)日：1999-09-07

申请号：US62175

申请日：1998-04-16

申请人： Lawrence Liu ,  Li-Chun Li ,  Michael Murray

发明人： Lawrence Liu ,  Li-Chun Li ,  Michael Murray

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1051

摘要： An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.

摘要翻译： 在MOS存储器件中使用的输入/输出偏置电路对无意的电源变化不敏感。 被编程为给定状态的存储器单元具有连接到第一节点的终端。 第一个MOS开关，常开，连接在第一个节点和一个接地端子之间。 常闭的偏置电路和第二MOS开关连接在电源端子和第一节点之间。 第一节点连接到读出放大器的两个输入端之一，第二输入端连接到读出放大器使能/禁止信号。 在选择存储单元时，第一开关被接通并且第二开关在第一时间段被关闭。 在此期间，偏置电路和第一开关相互作用以将第一节点偏置到等于低于电源电压的一个阈值电压的电位。 在第一时间段之后的第二时间段内，两个开关1和2都断开。 在此期间，偏置电路与存储器单元交互以将第一节点偏置到与存储器单元的状态相对应的电位。 而且在第二时段期间，读出放大器能够通过感测第一节点上的电位来检测存储器单元的状态。

公开(公告)号：US5812474A

公开(公告)日：1998-09-22

申请号：US733858

申请日：1996-10-18

申请人： Lawrence Liu ,  Li-Chun Li ,  Michael Murray

发明人： Lawrence Liu ,  Li-Chun Li ,  Michael Murray

IPC分类号： G11C7/10 ,  G11C7/02

CPC分类号： G11C7/1048

摘要： An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.

公开(公告)号：US5907257A

公开(公告)日：1999-05-25

申请号：US853291

申请日：1997-05-09

申请人： Lawrence Liu ,  Michael A. Murray ,  Li-Chun Li

发明人： Lawrence Liu ,  Michael A. Murray ,  Li-Chun Li

IPC分类号： G05F1/46 ,  G05F1/10

CPC分类号： G05F1/468 ,  G05F1/465

摘要： A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude. The intermediate value reduces the likelihood of latch-up during power-up, but the intermediate value does not go beyond the target value thus does not create a significant pn-junction current leakage in semiconductor regions to which the bias voltage is applied.

摘要翻译： 偏置电压发生器为不同的外部电源电压EVCC产生相同的偏置电压VBB（例如，对于EVCC = 3.3V或5.0V）。 在上电期间，产生VBB的电荷泵由参考EVCC的使能信号ExtEn控制。 之后，内部电源电压IVCC完全发展为独立于EVCC（例如，IVCC = 3.0V）的值，并且电荷泵由参考IVCC的使能信号IntEn控制。 该启用信号IntEn将使VBB达到其目标值，例如-1.5V。 该目标值与EVCC无关。 在上电期间，当电荷泵由ExtEn控制时，偏置电压VBB被驱动到中间值（例如，-0.5V或-1V）。 该中间值取决于EVCC，但是在大小上低于目标值。 中间值降低了在上电期间闭锁的可能性，但是中间值不超过目标值，因此在施加偏置电压的半导体区域中不会产生显着的pn结电流泄漏。

公开(公告)号：US06721224B2

公开(公告)日：2004-04-13

申请号：US10228530

申请日：2002-08-26

申请人： Steve S. Eaton ,  Michael Murray ,  Li-Chun Li

发明人： Steve S. Eaton ,  Michael Murray ,  Li-Chun Li

IPC分类号： G11C700

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C2211/4061

摘要： A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

摘要翻译： 只有在读取操作结束时或存储器被禁用但应保留数据处于禁用状态时，存储器才会执行隐藏刷新。 当存储器处于使能状态时，刷新不会在读取以外的任何操作结束时执行。 这是为了确保任何存储器访问命令的执行不会被刷新延迟，只要用户遵循特定的时序规则。 还提供了其他实施例。

公开(公告)号：US20050036346A1

公开(公告)日：2005-02-17

申请号：US10640928

申请日：2003-08-14

申请人： Youngweon Kim ,  Li-Chun Li

发明人： Youngweon Kim ,  Li-Chun Li

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12

CPC分类号： G11C16/3486 ,  G11C5/147 ,  G11C16/12

摘要： A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

摘要翻译： 诸如闪存EPROM的存储器包括写入电路（58和60），其调整向连接到单元组的存储器单元（50）的写入导体（92）提供多少电流或/和电压，以用于同时写入位 作为这些位中有多少处于一对相反的逻辑状态中的一个的函数的诸如字或字节的位组合到该单元组的单元中。

公开(公告)号：US06777280B2

公开(公告)日：2004-08-17

申请号：US10136498

申请日：2002-04-30

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

公开(公告)号：US06674669B2

公开(公告)日：2004-01-06

申请号：US10268863

申请日：2002-10-09

申请人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

发明人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C8/08

摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

摘要翻译： 在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。 每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。 此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。 如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

公开(公告)号：US06373778B1

公开(公告)日：2002-04-16

申请号：US09493299

申请日：2000-01-28

申请人： Jin Seung Song ,  Li-Chun Li

发明人： Jin Seung Song ,  Li-Chun Li

IPC分类号： G11C800

CPC分类号： G11C7/1027 ,  G11C7/1051 ,  G11C8/10 ,  G11C8/12

摘要： In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

摘要翻译： 在突发操作中，计数器接收一个或多个起始列地址的位。 由计数器产生的计数信号提供给列解码器。 列解码器响应于计数信号的单个值选择两列。 两列可以在非连续的列地址。 或者，两列可以在从奇数列地址边界开始的连续列地址处。 数据在两列和一个缓冲器之间并行传输。 数据在缓冲区和数据终端之间串行传输。 一些实施例适用于由同步动态随机存取存储器的标准定义的突发操作。