公开(公告)号：US6093951A

公开(公告)日：2000-07-25

申请号：US885102

申请日：1997-06-30

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7834

摘要： Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

摘要翻译： 公开了具有分级浓度分布的口袋区域的低阈值非对称MOS器件。 袋区域包括与器件的沟道区域相对的源或漏侧的器件的源极或漏极的相对高的掺杂剂原子浓度（与体区相同的导电类型）。 口袋区域的渐变浓度分布在基底表面附近提供较低的掺杂剂浓度，并且在该表面下方增加的掺杂剂浓度。 这提供了通过袋区域的相对较低的电阻传导路径，同时允许器件的阈值电压在口袋区域稍高一些。 不对称装置还可以包括位于其衬底表面下方的反掺杂剂区域。 这迫使电流在衬底中流动，但刚好高于高对位掺杂剂浓度的区域，其中电阻相对较低。

公开(公告)号：US5942781A

公开(公告)日：1999-08-24

申请号：US92973

申请日：1998-06-08

申请人： James B. Burr ,  Theodore W. Houston

发明人： James B. Burr ,  Theodore W. Houston

IPC分类号： H01L23/528 ,  H01L27/12 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S257/901

摘要： A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor substrate and extends across the conductive well. A transistor is formed on the insulating layer such that the insulating layer is interposed between the transistor and the semiconductor substrate, with the transistor including source and drain regions of the first conductivity type formed on the insulating layer, a channel region of a second conductivity type formed on the insulating layer and aligned over the conductive well, and a gate electrode aligned over the channel region. A metal contact is connected to the conductive well for applying a reverse bias potential to the transistor.

摘要翻译： 完全耗尽的SOI器件包括半导体衬底和形成在半导体衬底的主表面中的第一导电类型的导电阱。 绝缘层沿着半导体衬底的主表面形成并延伸穿过导电阱。 晶体管形成在绝缘层上，使得绝缘层插入在晶体管和半导体衬底之间，晶体管包括形成在绝缘层上的第一导电类型的源区和漏区，第二导电类型的沟道区 形成在绝缘层上并对准导电阱，以及在沟道区上对齐的栅电极。 金属触点连接到导电阱以向晶体管施加反向偏置电位。

公开(公告)号：US5650340A

公开(公告)日：1997-07-22

申请号：US456048

申请日：1995-05-31

申请人： James B. Burr ,  Michael P. Brassington

发明人： James B. Burr ,  Michael P. Brassington

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

摘要： Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An asymmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

摘要翻译： 本文公开了具有不对称晕轮植入物的低阈值电压MOS器件。 非对称晕轮植入物提供位于器件源极或漏极附近的位于源极（或漏极）边缘靠近器件的沟道区域的口袋区域。 口袋区域具有与器件体积相同的导电类型（尽管具有较高的掺杂剂浓度），当然还有与器件的源极和漏极相反的导电类型。 只有源或漏极，而不是两者都具有初级口袋区域。 不对称的晕圈器件类似于两个串联的伪MOS器件：“源FET”和“漏极FET”。 如果袋式注入位于源极之下，源FET将具有比漏极FET更高的阈值电压和更短的有效沟道长度。

公开(公告)号：US5622880A

公开(公告)日：1997-04-22

申请号：US414621

申请日：1995-03-31

申请人： James B. Burr ,  Michael P. Brassington

发明人： James B. Burr ,  Michael P. Brassington

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

摘要： Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

摘要翻译： 本文公开了具有埋电极的低阈值电压MOS器件。 这样的器件具有包括尖端区域和插塞区域的源极和漏极区域。 掩埋电极具有位于插塞区域的底部之上的底部边界。 掩埋电极具有与器件的体积相同的导电类型（尽管在较高的掺杂剂浓度），当然，与器件的源极和漏极相反的导电类型。 应提供掩埋电极的确切掺杂剂浓度和位置，使MOS器件避免穿通。