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    RECEIVER PROCESSING SYSTEM
    121.
    发明申请
    RECEIVER PROCESSING SYSTEM 审中-公开
    接收处理系统

    公开(公告)号：US20080130720A1

    公开(公告)日：2008-06-05

    申请号：US11946739

    申请日：2007-11-28

    Applicant: Anthony Craig Dolwin

    Inventor： Anthony Craig Dolwin

    IPC: H04B1/707

    CPC classification number: H04B1/7113 ,  H04B1/709 ,  H04B1/7115 ,  H04B1/7117 ,  H04B2201/70707 ,  H04B2201/7071 ,  H04B2201/70711

    Abstract: A method of adjusting the relative timing of a spreading sequence and a sampled input signal for a spread spectrum receiver correlator, the spreading sequence having an associated spreading sequence chip clock, the input signal being sampled at sample clock intervals, the method comprising: delaying the sampled input signal by an integral number of sample clock intervals to provide a fine relative timing adjustment; and delaying the spreading sequence by an integral number of spreading sequence chip clock periods to provide a coarse relative timing adjustment.

    Abstract translation: 一种调整扩展序列的相对定时和扩展频谱接收机相关器的采样输入信号的方法，该扩展序列具有相关联的扩频序列码片时钟，该输入信号以采样时钟间隔采样，该方法包括： 采样输入信号以整数个采样时钟间隔提供精确的相对定时调整; 并且将扩展序列延迟整数倍的扩展序列码片时钟周期，以提供粗略的相对定时调整。

    Method and apparatus for joint detection
    123.
    发明申请
    Method and apparatus for joint detection 有权
    联合检测方法和装置

    公开(公告)号：US20080080638A1

    公开(公告)日：2008-04-03

    申请号：US11545857

    申请日：2006-10-11

    Applicant: Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber ,  John Zijun Shen

    Inventor： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber ,  John Zijun Shen

    IPC: H04L25/49

    CPC classification number: H04B1/7105 ,  H04B2201/70711

    Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    Abstract translation: 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。

    Processor-implemented RAKE receiver
    125.
    发明授权
    Processor-implemented RAKE receiver 有权
    处理器实现的RAKE接收器

    公开(公告)号：US07298775B1

    公开(公告)日：2007-11-20

    申请号：US10651827

    申请日：2003-08-29

    Applicant: Tushar Shah ,  Manouchehr Rafie

    Inventor： Tushar Shah ,  Manouchehr Rafie

    IPC: H04B1/00

    CPC classification number: H04B1/7115 ,  H04B1/7117 ,  H04B2201/70711

    Abstract: A SWP- (Sub-Word Parallelism-) based RAKE receiver for a Wideband Code-Division Multiple Access (WCDMA) mobile station is optimized to perform channel de-rotation and data combining. The RAKE receiver comprises SIMD (Single Instruction, Multiple Data) instructions, which can perform a complex multiplication for a channel de-rotation in a single cycle. The SIMD instructions can also perform a complex addition for data combining in a single cycle. Optimization of the RAKE receiver reduces power consumption and costs, enhances performance, and provides extensibility for next-generation architectures.

    Abstract translation: 用于宽带码分多址（WCDMA）移动台的基于SWP-（子字平行）的RAKE接收机被优化以执行信道去旋转和数据组合。 RAKE接收机包括SIMD（单指令，多数据）指令，其可以在单个周期中对通道去旋转执行复数乘法。 SIMD指令还可以在单​​个周期中对数据合并进行复杂的加法。 RAKE接收机的优化降低了功耗和成本，提高了性能，并为下一代架构提供了可扩展性。

    Wireless spread spectrum communication platform using dynamically reconfigurable logic
    126.
    发明授权
    Wireless spread spectrum communication platform using dynamically reconfigurable logic 有权
    无线扩频通信平台采用动态可重构逻辑

    公开(公告)号：US07254649B2

    公开(公告)日：2007-08-07

    申请号：US11198692

    申请日：2005-08-05

    Applicant: Ravi Subramanian ,  Uma Jha ,  Joel D. Medlock

    Inventor： Ravi Subramanian ,  Uma Jha ,  Joel D. Medlock

    IPC: G06F13/10 ,  H04B1/38

    CPC classification number: H04B1/0003 ,  H04B1/707 ,  H04B2201/7071 ,  H04B2201/70711

    Abstract: A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

    Abstract translation: 本文公开了一种用于处理通信信号的无线扩频通信平台。 无线通信平台包括第一计算元件，第二计算元件和可重构互连。 第一计算元件经由可重构互连耦合到第二计算元件。 关于第二计算元件的设计配置，第一计算元件的设计配置是异构的。 可重配置互连具有未提交的架构，从而允许其由外部源配置以将第一可重配置互连的部分以各种组合耦合第二可重配置互连的部分。 第一计算元件，第二计算元件和可重构互连可操作以执行适于处理通信信号的离散功能。

    Universal rake receiver
    128.
    发明授权
    Universal rake receiver 有权

    公开(公告)号：US07106784B2

    公开(公告)日：2006-09-12

    申请号：US10057430

    申请日：2002-01-25

    Applicant: Ahmed Eltawil ,  Babak Daneshrad

    Inventor： Ahmed Eltawil ,  Babak Daneshrad

    IPC: H04B1/69 ,  H04B1/707

    CPC classification number: H04B1/709 ,  H04B1/712 ,  H04B7/0842 ,  H04B2201/70711

    Abstract: A universal rake receiver architecture includes modular independent processing units that can be flexibly programmed to support different modes of operation. The processing units are capable of performing the basic correlation calculations of DS-CDMA and each unit has an internal local memory and controller that controls its mode of operation. Each unit performs the required synchronization and demodulation operations for a multipath of a signal in the digital domain using all-digital frequency and timing correction techniques. Frequency feedback need not be supplied to the analog section of the receiver. Interpolation most preferably is used to find the optimum sampling position of each incoming chip. This independence allows the receiver to be used with one to several antennas without design modifications.

    Correlation architecture for use in software-defined radio systems
    129.
    发明申请
    Correlation architecture for use in software-defined radio systems 有权

    公开(公告)号：US20060184599A1

    公开(公告)日：2006-08-17

    申请号：US11150511

    申请日：2005-06-10

    Applicant: Yan Wang ,  Eran Pisek ,  Jasmin Oz

    Inventor： Yan Wang ,  Eran Pisek ,  Jasmin Oz

    IPC: G06F17/15

    CPC classification number: H04B1/707 ,  G06F17/15 ,  H04B1/709 ,  H04B2201/7071 ,  H04B2201/70711

    Abstract: A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a−b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and −1 and 2) the difference (a−b) multiplied by one of +1 and −1.

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