公开(公告)号：US11252464B2

公开(公告)日：2022-02-15

申请号：US16850036

申请日：2020-04-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Michael Kagan

IPC: H04N21/00 ,  H04N21/426 ,  G06T1/60

Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

公开(公告)号：US11190462B2

公开(公告)日：2021-11-30

申请号：US16693302

申请日：2019-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis

IPC: G06F15/16 ,  H04L12/939 ,  H04L12/861 ,  H04W28/04 ,  H04L29/06 ,  H04L12/879

Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

公开(公告)号：US11057637B1

公开(公告)日：2021-07-06

申请号：US16775463

申请日：2020-01-29

Applicant: Mellanox Technologies, Ltd. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Tamar Shoham

IPC: H04N19/52 ,  H04N19/177 ,  H04N19/176

Abstract: A video processor includes a memory and a processor. The processor is coupled to memory and is configured to store in the memory (i) multiple raw frames belonging to a Group of Pictures (GOP) to be processed, and (ii) one or more reference frames. The processor is further configured to select for multiple target blocks having a same block-location in respective raw frames associated with a common reference frame, a common search region in the common reference frame, and before selecting another search region, to apply at least two motion estimation operations using at least two of the target blocks and the common search region, to estimate respective at least two Motion Vectors (MVs).

公开(公告)号：US20200314181A1

公开(公告)日：2020-10-01

申请号：US16827912

申请日：2020-03-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

IPC: H04L29/08

Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

公开(公告)号：US20200245016A1

公开(公告)日：2020-07-30

申请号：US16850036

申请日：2020-04-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Michael Kagan

IPC: H04N21/426 ,  G06T1/60

Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

公开(公告)号：US20200014918A1

公开(公告)日：2020-01-09

申请号：US16291023

申请日：2019-03-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/139

Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce a score of result blocks based on similarity of each the block in each frame to be encoded to every block of the reference frame, and a displacement vector. Related apparatus and methods are also provided.