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公开(公告)号:US11438588B2
公开(公告)日:2022-09-06
申请号:US16942081
申请日:2020-07-29
Inventor: Ryuichi Kanoh , Tadamasa Toma , Kiyofumi Abe , Takahiro Nishi
IPC: H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry in operation: determines whether the shape of a current chroma block to be split satisfies a first condition; generates one or more second candidates for a block partitioning method by eliminating one or more predetermined candidates from a plurality of first candidates for a block partitioning method when the current chroma block satisfies the first condition; selects a block partitioning method from among the one or more second candidates; and splits the current chroma block according to the block partitioning method selected.
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公开(公告)号:US11425385B2
公开(公告)日:2022-08-23
申请号:US17173024
申请日:2021-02-10
Inventor: Yusuke Kato , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/13 , H04N19/176 , H04N19/46 , H04N19/169
Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.
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公开(公告)号:US11350111B2
公开(公告)日:2022-05-31
申请号:US17196194
申请日:2021-03-09
Inventor: Jing Ya Li , Ru Ling Liao , Chong Soon Lim , Han Boon Teo , Hai Wei Sun , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/159 , H04N19/117 , H04N19/182
Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of gradient values in first and second ranges; derives, as a first parameter, a total sum of absolute values of sums of gradient values derived respectively for pairs of relative pixel positions; derives a pixel difference value between pixel values in the first and second ranges; inverts or maintains a plus or minus sign of the pixel difference value, according to a plus or minus sign of the sum of the gradient values indicating the sum of the gradient values in the first and second ranges; derives, as a second parameter, a total sum of pixel difference values each having the plus or minus sign inverted or maintained, the pixel difference values derived respectively for the relative pixel positions; and generates a prediction image using the first and second parameters.
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公开(公告)号:US11284136B2
公开(公告)日:2022-03-22
申请号:US17034248
申请日:2020-09-28
Inventor: Noritaka Iguchi , Tadamasa Toma , Hisaya Katou
IPC: H04N21/236 , H04N21/434 , H04N19/169 , H04N21/854 , G10L19/16 , H04N19/436 , H04N19/70 , H04N5/38 , H04N5/44
Abstract: A transmitting method according to one aspect of the present disclosure includes: encoding a video signal and generating encoded data including a plurality of access units; storing the plurality of access units in a packet in a unit that defines one access unit as one unit or in a unit defined by dividing one access unit, and generating a packet group; transmitting the generated packet group as data; generating first information and second information, the first information indicating a presentation time of a first access unit that is presented first among the plurality of access units, and the second information being used to calculate a decoding time of the plurality of access units; and transmitting the first information and the second information as control information.
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公开(公告)号:US11233993B2
公开(公告)日:2022-01-25
申请号:US16590776
申请日:2019-10-02
Inventor: Ryuichi Kanoh , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/14 , H04N19/117 , H04N19/159 , H04N19/174
Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. The processing circuitry is configured to: select a first filter for a first block based at least on a prediction mode used for the first block, the first filter including a first set of filter coefficients; select a second filter for a second block, the second filter including a second set of filter coefficients; and change values of pixels in the first block and the second block to filter a boundary between the first block and the second block, by multiplying the values of pixels in the first block by the first set of filter coefficients, respectively, and multiplying the values of pixels in the second block by the second set of filter coefficients, respectively, the pixels in the first block and the second block being arranged along a line across the boundary.
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公开(公告)号:US11206410B2
公开(公告)日:2021-12-21
申请号:US17031087
申请日:2020-09-24
Inventor: Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh
IPC: H04N19/159 , H04N19/105 , H04N19/176 , H04N19/186 , H04N19/583
Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.
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公开(公告)号:US11172198B2
公开(公告)日:2021-11-09
申请号:US16590773
申请日:2019-10-02
Inventor: Ryuichi Kanoh , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/117 , H04N19/103 , H04N19/176 , H04N19/182
Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. The processing circuitry is configured to: select a first filter for a first block based at least on a block size of the first block, the first filter including a first set of filter coefficients; select a second filter for a second block based at least on a block size of the second block, the second filter including a second set of filter coefficients; and change values of pixels in the first block and the second block to filter a boundary between the first block and the second block. The first set of filter coefficients applied in the first block and the second set of filter coefficients applied in the second block are selected to be asymmetrical with respect to the boundary based on the block size of the first block and the second block.
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公开(公告)号:US11166026B2
公开(公告)日:2021-11-02
申请号:US16192070
申请日:2018-11-15
Inventor: Takahiro Nishi , Tadamasa Toma , Kiyofumi Abe
IPC: H04N19/13 , H04N19/70 , H04N19/172 , H04N19/174 , H04N19/91 , H04N19/124 , H04N19/159
Abstract: An encoder is an encoder which encodes image information and includes memory and circuitry accessible to the memory. The circuitry derives, from the image information, a binary data string according to binarization for arithmetic encoding, and outputs a bit stream including the binary data string and application information indicating whether or not the binary data string has been arithmetic encoded. The circuitry outputs, as the bit stream, a string including as the binary data string, a data string which has not been arithmetic encoded; and, as the application information, information indicating that the binary data string has not been arithmetic encoded.
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公开(公告)号:US11146811B2
公开(公告)日:2021-10-12
申请号:US16682749
申请日:2019-11-13
Inventor: Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh
IPC: H04N19/537 , H04N19/105 , H04N19/157 , H04N19/52 , H04N19/573
Abstract: An encoder includes memory and circuitry. The circuitry: derives a first motion vector in a unit of a prediction block using a first inter frame prediction mode that uses a degree of matching between two reconstructed images of two regions in two difference pictures, the prediction block being obtained by splitting an image included in a video; and performs, in the unit of the prediction block, a first motion compensation process that generates a prediction image by referring to a spatial gradient of luminance in an image generated by performing motion compensation using the first motion vector derived.
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公开(公告)号:US11115654B2
公开(公告)日:2021-09-07
申请号:US16901869
申请日:2020-06-15
Inventor: Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh
IPC: H04N19/119 , H04N19/105 , H04N19/139 , H04N19/14 , H04N19/176 , H04N19/52 , H04N19/573
Abstract: An encoder is disclosed which includes circuitry and memory. Using the memory, the circuitry, in a first operating mode, derives first motion vectors for a first block obtained by splitting a picture, and generates a prediction image corresponding to the first block, with a bi-directional optical flow flag settable to true, and by referring to spatial gradients of luminance generated based on the first motion vectors. Using the memory, the circuitry, in a second operating mode, derives second motion vectors for a sub-block obtained by splitting a second block, the second block being obtained by splitting the picture, and generates a prediction image corresponding to the sub-block, with the bi-directional optical flow flag set to false.
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