公开(公告)号：US12132904B2

公开(公告)日：2024-10-29

申请号：US17503524

申请日：2021-10-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N7/12 ,  H04N19/12 ,  H04N19/13 ,  H04N19/167 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/13 ,  H04N19/12 ,  H04N19/167 ,  H04N19/176 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In residual coding of a current block, the circuitry, in operation, encodes a subblock flag by Context-based Adaptive Binary Arithmetic Coding (CABAC) in both of a first type of residual coding where an orthogonal transform is performed and a second type of residual coding where the orthogonal transform is skipped, the subblock flag indicating whether a non-zero coefficient is included in a plurality of coefficients for a subblock within the current block, wherein a first syntax used for the first type of residual coding is different from a second syntax used for the second type of residual coding; and controls a number of CABAC processes, wherein the encoding of the subblock flag is not counted as the number of CABAC processes.

公开(公告)号：US12120291B2

公开(公告)日：2024-10-15

申请号：US17944866

申请日：2022-09-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling Liao ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Sughosh Pavan Shashidhar ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.

公开(公告)号：US12113978B2

公开(公告)日：2024-10-08

申请号：US18214653

申请日：2023-06-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/12 ,  H04N19/124 ,  H04N19/176 ,  H04N19/625

CPC classification number: H04N19/12 ,  H04N19/124 ,  H04N19/176 ,  H04N19/625

Abstract: When a transform-basis adaptive selection mode is enabled, an encoder that transforms residuals of a current block to encode an image: adaptively selects a first horizontal transform basis from among one or more transform basis candidates when a horizontal size of the current block is greater than a first horizontal threshold size; otherwise selects a fixed horizontal transform basis as a first horizontal transform basis; adaptively selects a first vertical transform basis from among the one or more transform basis candidates when a vertical size of the current block is greater than a first vertical threshold size; otherwise selects a fixed vertical transform basis as a first vertical transform basis; and generates first transform coefficients by performing a first horizontal transform and a first vertical transform on the residuals of the current block, using the first horizontal transform basis selected and the first vertical transform basis selected, respectively.

公开(公告)号：US12108080B2

公开(公告)日：2024-10-01

申请号：US18224143

申请日：2023-07-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/96 ,  H04N19/159 ,  H04N19/176 ,  H04N19/44 ,  H04N19/593 ,  H04N19/66

CPC classification number: H04N19/593 ,  H04N19/176 ,  H04N19/44

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: prohibits a first splitting method when arrangement and shapes of blocks obtained by splitting a first block multiple times by the first splitting method are identical to arrangement and shapes of blocks obtained by splitting the first block multiple times by a second splitting method different from the first splitting method, and when scan order of the blocks obtained by the first splitting method is identical to scan order of the blocks obtained by the second splitting method; and encodes the first block.

公开(公告)号：US12081749B2

公开(公告)日：2024-09-03

申请号：US18142166

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

Abstract: An encoder that encodes a current block to be encoded in an image is provided. The encoder includes: processor; and memory coupled to the processor, in which, in operation, the processor: generates a first prediction image based on a motion vector, the first prediction image being an image with full-pel precision; generates a second prediction image using an interpolation filter by interpolating a value at a fractional-pel position between full-pel positions included in the first prediction image; and encodes the current block based on the second prediction image, and in the using of the interpolation filter, the interpolation filter is switched between a first interpolation filter and a second interpolation filter differing in a total number of taps from the first interpolation filter.

公开(公告)号：US12052442B2

公开(公告)日：2024-07-30

申请号：US18133070

申请日：2023-04-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/169 ,  H04N19/423 ,  H04N19/46

CPC classification number: H04N19/70 ,  H04N19/188 ,  H04N19/423 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: writes, into a sequence parameter set which is header information of a sequence, video usability information syntax which is information for realizing an additional function in display of an image, and syntax different from the video usability information syntax. The syntax includes at least one parameter related to display timing of the image.

公开(公告)号：US12052436B2

公开(公告)日：2024-07-30

申请号：US18142173

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Takashi Hashimoto

IPC: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.

公开(公告)号：US12028519B2

公开(公告)日：2024-07-02

申请号：US18071370

申请日：2022-11-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/105 ,  H04N19/117 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186

CPC classification number: H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US12028513B2

公开(公告)日：2024-07-02

申请号：US17463889

申请日：2021-09-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder includes: circuitry; and memory coupled to the circuitry, in which in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size.

公开(公告)号：US12022072B2

公开(公告)日：2024-06-25

申请号：US17992833

申请日：2022-11-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei Sun ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

CPC classification number: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component, and clips the second coefficient value. The circuitry generates a third coefficient value by adding the first coefficient value to the clipped second coefficient value, and clips the third coefficient value. The circuitry encodes a third reconstructed image sample of the chroma component using the clipped third coefficient value.