Abstract:
A method and system for optimizing the behavior of a charger connected to a portable device when the portable device current exceeds the charger current limit. The system includes a configuration module configured to set a maximum current limit and a register-based current limit values. The system further includes a port power switch configured to limit the portable device current, in the event that the portable device current exceeds the maximum current limit value. The port power switch is configures to modify the portable device current to a predetermined constant current value or reset the current to zero based on the relation between the maximum current limit and the register-based current limit value.
Abstract:
A system and method are presented for aligning a rotor in a motor. The motor may include the rotor and a plurality of pairs of electromagnets. One or more pairs of electromagnets may be excited at a first excitation level. The one or more pairs of electromagnets may be less than all of the plurality of pairs of electromagnets. The excitation of the one or more pairs of electromagnets may be increased to a second excitation level over a first period of time. The excitation of the one or more pairs of electromagnets may be decreased to a third excitation level over a second period of time. Exciting the one or more pairs of electromagnets, increasing the excitation, and decreasing the excitation may cause the rotor to stop in a known position.
Abstract:
A charging method and system for rationing charge or energy supplied by a host to a portable device. The system includes a power switch, and a current sensing module connected to the power switch. The current sensing module detects instantaneous current drawn by the portable device. The system further includes a current register connected to the current sensing module for storing the instantaneous current value. A timing module generates timing information. The system also includes a charge register storing a cumulative charge drawn by the portable device. The cumulative charge is obtained by multiplying the instantaneous current value with the timing information. A threshold database stores a threshold value, and a rationing module connected to the host and the charge register continuously compares the cumulative charge value with the threshold charge value. When the cumulative charge value exceeds the threshold charge value, a control signal is generated.
Abstract:
A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.
Abstract:
A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.
Abstract:
A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.
Abstract:
A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage.
Abstract:
A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a source for a read operation, configure the second slave device as a target for a write operation, provide a clock signal to both the first slave device and the second slave device, and initiate a read operation of the first slave device. Initiation of the read operation causes the first slave device to provide data onto the peripheral bus. Responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device. The master device is configured to ignore the data provided on the peripheral bus by the first slave device.
Abstract:
An input protection circuit (IPC) may prevent an input signal from propagating into a system, such as an integrated circuit (IC), when the voltage level of the input signal exceeds a specified value. The IPC may be configured to compare the input signal voltage, which may be that of an external input signal received by the system, with a reference voltage, which may be the power supply voltage. If the input signal voltage exceeds the reference voltage, the output of the IPC may be set to the value of a specified clamp voltage. If the input signal voltage does not exceed the reference voltage, the output of the IPC may track (or follow) the input signal voltage. For certain integrated circuits, the IPC may be configured to provide circuit protection for an input signal voltage ranging between 0V to 5V, and a power supply voltage ranging between 3.0V and 3.6V.
Abstract:
An integrated circuit may include one or more cells, with each cell comprising a first and a second input terminal, a first and a second output terminal, and a number of connection stages configured to couple each input terminal to a corresponding respective output terminal. The stages may include one stage per metal layer of the integrated circuit and one stage per VIA layer of the integrated circuit. Each stage may be configured with a pair of input ports and a pair of output ports. Each output port of a stage may serially connect to a corresponding respective input port of a first adjacent stage, and each input port of the stage may also serially connect to a corresponding respective output port of a second adjacent stage. The pair of input ports may also be configured to programmably connect to the pair of output ports within the same stage, according to one of two different connection patterns, to establish a respective connection within the stage. A combination of the respective connections within the stages may determine which input terminal of the cell connects to which output terminal of the cell.