公开(公告)号：US12188483B2

公开(公告)日：2025-01-07

申请号：US18117013

申请日：2023-03-03

Applicant: ASUSTEK COMPUTER INC.

Inventor： Hsin Chen Lin ,  Ing-Jer Chiou

IPC: F04D29/42 ,  F04D17/16 ,  F04D29/28

Abstract: The disclosure provides a centrifugal fan including a housing and a blade module. The housing includes a lower cover, a side wall, and an upper cover. Two ends of the side wall are respectively connected to the lower cover and the upper cover to define an internal space. The lower cover includes a plurality of lower air inlets. The blade module is arranged in the internal space, and includes a hub and a plurality of blades. The hub is rotatably arranged on the lower cover. The blades are arranged around the hub. The lower air inlets are located on the periphery of the hub, and each lower air inlet includes an outer edge relative to a rotational axis of the hub. At least one of two ends of at least one of the lower air inlets includes a protruding portion at a position corresponding to the outer edge.

公开(公告)号：US12184180B2

公开(公告)日：2024-12-31

申请号：US17984221

申请日：2022-11-09

Applicant: ASUSTeK COMPUTER INC.

Inventor： Wei Kao ,  Ming-Ting Tsai ,  Hsiang-Jui Hung ,  Hsi-Ho Hsu ,  Chen-Hao Yu ,  Chun-San Lin ,  Wei-Gen Chung

IPC: H02M1/088 ,  H02M1/14 ,  H02M3/158

Abstract: A power supply phase doubling system includes a pulse width modulation (PWM) controller and first and second phase doubling chips. The PWM controller outputs a PWM signal. The first phase doubling chip is operated at a power supply voltage and has a first PWM output pin to generate a first control signal and a second control signal according to the PWM signal, and generates a first output signal according to the first control signal. The second phase doubling chip is operated at the power supply voltage, has a second PWM output pin, and is configured to generate a second output signal according to the second control signal. The first and second phase doubling chips are respectively switched between a master mode and a slave mode according to a voltage level of the first PWM output pin and a voltage level of the second PWM output pin.

公开(公告)号：US20240402770A1

公开(公告)日：2024-12-05

申请号：US18454078

申请日：2023-08-23

Applicant: ASUSTeK COMPUTER INC.

Inventor： Kunsu Zhang ,  Wen-Ting Yu ,  Zhaowei Sheng ,  Feng Huang

IPC: G06F1/18 ,  H05K1/14

Abstract: A fixing assembly is suitable for being arranged on a circuit board and configured to fix an expansion card. The fixing assembly includes a body and a buckle structure. The buckle structure includes a pressing part, a buckle part, an elastic member, and a base. The pressing part is away from the circuit board. An end of the buckle part is connected to the pressing part and has an inclined surface and a blocking surface connected to each other. The blocking surface has a gap with the top surface. The elastic member is connected to another end of the buckle part. When a first end of the expansion card is connected to the connector, a second end of the expansion card slides along the inclined surface to the top surface and is fixed in the gap by being abutted by the blocking surface.

公开(公告)号：US12141006B2

公开(公告)日：2024-11-12

申请号：US17828577

申请日：2022-05-31

Applicant: ASUSTEK COMPUTER INC.

Inventor： Chih-Yao Kuo ,  Ya-Han Chang ,  Huang-Chieh Huang

IPC: G06F1/28 ,  G06F9/50

Abstract: A power management method for an electronic device is provided. The electronic device includes a processing unit with a core and configured to execute an application program and a functional element. The power management method includes the following steps: determining a maximum frame count per second of a scene; down-tuning a frequency setting value of the core; detecting an actual frame count per second of the scene; determining a change in power consumption of the processing unit and a temperature of the functional element when the actual frame count per second is equal to the maximum frame count per second; and down-tuning the frequency setting value when the power consumption does not increase and the temperature is lower than a preset temperature value, and restoring the frequency setting value when the power consumption increases or the temperature is higher than or equal to the preset temperature value.

公开(公告)号：US12133181B2

公开(公告)日：2024-10-29

申请号：US17560546

申请日：2021-12-23

Applicant: ASUSTek Computer Inc.

Inventor： Yi-Hsuan Kung ,  Yu-Hsuan Guo ,  Chun-Wei Huang

IPC: H04W52/36 ,  H04L5/00 ,  H04W72/23

CPC classification number: H04W52/365 ,  H04L5/0048 ,  H04W72/23

Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives an uplink (UL) grant. The UL grant is indicative of a first Physical Uplink Shared Channel (PUSCH) transmission on a first Transmission/Reception Point (TRP) of a first cell. The UL grant is not indicative of a PUSCH transmission on a second TRP of the first cell. The UE transmits a Power Headroom Reporting (PHR) Medium Access Control (MAC) Control Element (CE). Based on the UL grant, the PHR MAC CE is indicative of a first power headroom (PH), associated with the first TRP, based on a real PUSCH transmission, and is indicative of a second PH, associated with the second TRP, based on a reference PUSCH transmission.

公开(公告)号：US20240320871A1

公开(公告)日：2024-09-26

申请号：US18406197

申请日：2024-01-07

Applicant: ASUSTeK COMPUTER INC.

Inventor： I-Chang Lee ,  Yi-Chen Lin ,  Chien-Yi Wang

IPC: G06T11/00 ,  G06T3/60 ,  G06V10/774

CPC classification number: G06T11/00 ,  G06T3/60 ,  G06V10/774

Abstract: An image generation method and an image generation device are disclosed. The method includes: reading a first image from a storage circuit; disposing an image mask on the first image, wherein the image mask covers a part of the image areas in the first image; moving, randomly, the image mask to change a covering range of the image mask in the first image; obtaining a second image from the first image according to the moved image mask; and storing the second image into the storage circuit.

公开(公告)号：US20240314960A1

公开(公告)日：2024-09-19

申请号：US18317936

申请日：2023-05-16

Applicant: ASUSTeK COMPUTER INC.

Inventor： Wei-Chia Liao ,  Wen-Ting Yu ,  Chin-Chuan Wu ,  Yi-Min Hsu

IPC: H05K7/14 ,  H05K1/14 ,  H05K5/02

CPC classification number: H05K7/1429 ,  H05K1/141 ,  H05K5/0295

Abstract: A circuit board is adapted for inserting an expansion card with an electrical contact part, a non-electrical convex part, and a positioning part. The circuit board includes a board body, a slot, a release structure, and a transmission mechanism. The slot is disposed on the board body and includes a socket, a connecting end, and an outer surface. The socket is adapted for the electrical contact part to be inserted. The release structure is movably disposed at the connecting end and includes a limiting part. The transmission mechanism is disposed in the socket, adjacent to the connecting end, or adjacent to the outer surface. The transmission mechanism includes a driving member and a linking member. The driving member is adapted for contacting the electrical contact part, the non-electrical convex part, or the positioning part. The linking member is disposed between the driving member and the release structure.

公开(公告)号：US12096070B2

公开(公告)日：2024-09-17

申请号：US17965128

申请日：2022-10-13

Applicant: ASUSTEK COMPUTER INC.

Inventor： Chieh Li

IPC: H04N21/44

CPC classification number: H04N21/44008

Abstract: A video editing method applied to an electronic device is provided. The electronic device includes a processor and a human-machine interface, the processor is configured to execute a program to generate video data, and the human-machine interface is configured to receive an input signal. The video editing method includes: obtaining the video data; monitoring the input signal; setting an editing condition; and recording the video data to generate a video clip when the input signal meets the editing condition. A video editing system is further provided.

公开(公告)号：US20240265845A1

公开(公告)日：2024-08-08

申请号：US18500374

申请日：2023-11-02

Applicant: ASUSTeK COMPUTER INC.

Inventor： Chen-Wei LIN ,  Chin-An TSENG ,  Yung-Ming HUANG

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2320/0242 ,  G09G2320/0626

Abstract: A method for reducing a color edge phenomenon of a display panel is provided. The method is applicable to a display panel including a plurality of pixel units. The method includes: performing pixel adjustment on the pixel units at edges of the display panel. Each pixel unit includes at least three sub-pixels: a first sub-pixel, a second sub-pixel, and a third sub-pixel. By adjusting positions, areas, or brightness of the sub-pixels, the color edge phenomenon of the display panel is effectively reduced or avoided.

公开(公告)号：US20240260050A1

公开(公告)日：2024-08-01

申请号：US18632383

申请日：2024-04-11

Applicant: ASUSTek Computer Inc.

Inventor： Chun-Wei Huang

IPC: H04W72/23 ,  H04L1/1812 ,  H04L1/1867 ,  H04W24/08 ,  H04W72/0453 ,  H04W72/1263 ,  H04W72/50

CPC classification number: H04W72/23 ,  H04L1/1819 ,  H04L1/1896 ,  H04W24/08 ,  H04W72/0453 ,  H04W72/1263 ,  H04W72/535

Abstract: A method and apparatus are disclosed. In an example, a User Equipment (UE) is configured with one or more cells including a second cell. The UE is configured to monitor one or more first UE-specific Physical Downlink Control Channels (PDCCHs) on the second cell. The one or more first UE-specific PDCCHs schedule data transmission on a first cell. The UE receives a Downlink Control Information (DCI) indicative of dormancy information associated with the one or more cells. The DCI indicates dormant status of the second cell. In response to the DCI indicating the dormant status of the second cell, the UE switches a scheduling cell of the first cell from the second cell to the first cell, and the UE monitors one or more second UE-specific PDCCHs on the first cell. The one or more second UE-specific PDCCHs schedule data transmission on the first cell.