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15 条记录 (耗时 0.012 秒)

    Portable telephone apparatus and stablly supplying method of reference frequency
    11.
    发明授权
    Portable telephone apparatus and stablly supplying method of reference frequency 失效
    便携式电话设备和参考频率稳定供电方式

    公开(公告)号：US06748199B2

    公开(公告)日：2004-06-08

    申请号：US09764054

    申请日：2001-01-19

    申请人： Akihiro Nakano

    发明人： Akihiro Nakano

    IPC分类号： H04B118

    CPC分类号： H03J7/026 ,  H04B1/403

    摘要： A portable telephone apparatus includes a reference frequency generating section capable of suitably changing frequency accuracy of an output signal in accordance with an input control voltage, and a high-accurate reference frequency generating section having accuracy for a temperature change extremely higher than that of the reference frequency generating section and in which output frequency accuracy thereof changes only within a range of prescribed values. A determination device determines whether or not frequency accuracy of an output signal from the reference frequency generating section meets the prescribed value. A selector selects an output signal from the reference frequency generating section in a case that a determination result of the determination device meets the prescribed value, and selects an output signal from the high-accurate reference frequency generating section in a case that a determination result of the determination device does not meet the prescribed value.

    摘要翻译： 一种便携式电话设备包括：能够根据输入控制电压适当地改变输出信号的频率精度的参考频率产生部分和具有比参考电压的温度变化极高的温度变化精度的高精度参考频率发生部分 频率产生部，其输出频率精度仅在规定值的范围内变化。 确定装置确定来自基准频率产生部分的输出信号的频率精度是否满足规定值。 在确定装置的确定结果满足规定值的情况下，选择器从参考频率产生部分选择输出信号，并且在确定结果的情况下选择来自高精度参考频率产生部分的输出信号 确定装置不符合规定值。

    CONTROL SYSTEM AND CPU UNIT
    14.
    发明申请
    CONTROL SYSTEM AND CPU UNIT 审中-公开
    控制系统和CPU单元

    公开(公告)号：US20110131348A1

    公开(公告)日：2011-06-02

    申请号：US12952470

    申请日：2010-11-23

    申请人： Akihiro Onozuka ,  Katsuhito Shimizu ,  Yusaku Otsuka ,  Yukiko Tahara ,  Masakazu Ishikawa ,  Eiji Kobayashi ,  Wataru Sasaki ,  Akihiro Nakano ,  Yuusuke Seki

    发明人： Akihiro Onozuka ,  Katsuhito Shimizu ,  Yusaku Otsuka ,  Yukiko Tahara ,  Masakazu Ishikawa ,  Eiji Kobayashi ,  Wataru Sasaki ,  Akihiro Nakano ,  Yuusuke Seki

    IPC分类号： G06F3/00

    CPC分类号： G05B15/02

    摘要： In the disclosed control system, loops of 1st path and 2nd path are formed connecting an active CPU unit and each of RIO units, the direction of data frame transfer through the loop of 1st path being opposite to that of the data frame transfer through the loop 2nd path. Reflective electro-optical transducer modules are used in the RIO units which are connected with the active CPU unit so that a standby CPU unit can also be connected. Further, the loop of 1st path and the loop of 2nd path are formed connecting the standby CPU module and each of the RIO modules. The data frame transfer directions through the loops connecting the active CPU unit and each of the RIO units are opposite to the data frame transfer directions through the corresponding loops connecting the standby CPU unit and each of the RIO units.

    摘要翻译： 在公开的控制系统中，形成连接有源CPU单元和RIO单元的第一路径和第二路径的环路，通过第一路径的循环的数据帧传输方向与通过循环的数据帧传输的方向相反的方向 第二条路。 在与主动CPU单元连接的RIO单元中使用反射式电光换能器模块，以便也可以连接备用CPU单元。 此外，连接备用CPU模块和每个RIO模块形成第一路径的循环和第二路径的循环。 通过连接主动CPU单元和每个RIO单元的回路的数据帧传送方向通过连接待机CPU单元和每个RIO单元的相应环路与数据帧传送方向相反。

    Voltage boosting circuit
    15.
    发明授权
    Voltage boosting circuit 有权
    升压电路

    公开(公告)号：US6147923A

    公开(公告)日：2000-11-14

    申请号：US343404

    申请日：1999-06-30

    申请人： Akihiro Nakano

    发明人： Akihiro Nakano

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/407 ,  H02M3/07 ,  G11C7/00

    CPC分类号： G11C5/145 ,  G11C8/08

    摘要： An NMOS capacitor 13 and a PMOS capacitor 18 for pumping up are connected in series to an output line 12. In middle point voltage control circuit 20, a power supply line at VCC is connected via a PMOS transistor 21 to the anode of a reverse-flow preventing diode 22 and the node of voltage VM, the cathode of the diode 22 is connected via an NMOS transistor 23 to a ground line, and control signals *BIN and AIN are provided to the gate electrodes of the transistors 21 and 23, respectively, in response to an address transition detection signal AT. An end point voltage control circuit 30 is connected between the gate electrode of the NMOS transistor 23 and one end of the PMOS capacitor 18, and is equipped with inverters 31 and 32 connected in series. In an initial state, VM is at 0V and VE and VOUT is at VCC. Next the node of VM becomes a floating state and VE is lowered to 0V. Finally the node of VM is raised to VCC to boost VOUT from VCC up to VCC(2+.alpha.), where 0

    摘要翻译： 用于泵浦的NMOS电容器13和PMOS电容器18串联连接到输出线12.在中点电压控制电路20中，VCC处的电源线经由PMOS晶体管21连接到反向电压的阳极， 流阻二极管22和电压VM的节点，二极管22的阴极经由NMOS晶体管23连接到接地线，并且控制信号* BIN和AIN分别提供给晶体管21和23的栅电极 响应于地址转换检测信号AT。 端点电压控制电路30连接在NMOS晶体管23的栅电极和PMOS电容器18的一端之间，并配有串联连接的反相器31,32。 在初始状态下，VM为0V，VE和VOUT为VCC。 接下来，VM的节点变为浮动状态，VE降低到0V。 最后，VM的节点被提升到VCC，以将VOUT从VCC升高到VCC（2+ alpha），其中0 <α<1。