公开(公告)号：US5812026A

公开(公告)日：1998-09-22

申请号：US705596

申请日：1996-08-30

Applicant: Alexander Fairgrieve

Inventor： Alexander Fairgrieve

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F2203/45352 ,  H03F2203/45584 ,  H03F2203/45641 ,  H03F2203/45648 ,  H03F2203/45696

Abstract: A circuit used with a differential amplifier to eliminate the effect of Early Voltage from voltage gain provided by the differential amplifier. With a differential amplifier utilizing PNP transistors which experience the lowest, and most undesirable Early Voltage, the circuitry includes a pair of transistors 400 and 402, each with a base connected to an input of the differential amplifier corresponding to a similar base connection of a respective one of transistors 100 and 102 of the differential amplifier, an emitter connected to a current source, and a collector connected to the collector of a respective one of NPN current sink transistors 306 and 308 connected at outputs of the differential amplifier. The circuitry for elimination of Early Voltage further includes components to assure the collector voltages of transistors 400 and 402 are equal and the collector voltages of transistors 102 and 400 are equal. In addition to circuitry for elimination of Early Voltage when PNP transistors 100 and 102 are used to provide the differential amplifier inputs, the circuitry may also be configured for use when NPN transistors provide inputs for a differential amplifier.

Abstract translation: 与差分放大器一起使用的电路，以消除由差分放大器提供的电压增益对早期电压的影响。 利用利用PNP晶体管的差分放大器，其经历最低和最不期望的早期电压，该电路包括一对晶体管400和402，每个晶体管400和402各自具有连接到差分放大器的输入，该输入对应于相应的基本连接 差分放大器的晶体管100和102中的一个，连接到电流源的发射极和连接到差分放大器的输出处的NPN电流吸收晶体管306和308中的相应一个的集电极的集电极。 用于消除早期电压的电路还包括确保晶体管400和402的集电极电压相等并且晶体管102和400的集电极电压相等的组件。 除了使用PNP晶体管100和102用于提供差分放大器输入以消除早期电压的电路之外，还可以将电路配置为在NPN晶体管为差分放大器提供输入时使用。

公开(公告)号：US5493254A

公开(公告)日：1996-02-20

申请号：US222213

申请日：1994-03-31

Applicant: Alexander Fairgrieve

Inventor： Alexander Fairgrieve

IPC: H03F1/14 ,  H03F1/56 ,  H03F3/45

CPC classification number: H03F1/56 ,  H03F1/14 ,  H03F3/45089 ,  H03F2203/45018 ,  H03F2203/45024 ,  H03F2203/45202 ,  H03F2203/45318 ,  H03F2203/45374 ,  H03F2203/45702

Abstract: The input capacitance of a differential amplifier is reduced by connecting a positive feedback path between the collector of each input transistor and a terminal of a resistor connected in the other parallel current path. The positive feedback paths cause the voltage at the collector of each input transistor to move in the same direction as the voltage at the base of that input transistor, and thereby reduce the effective input capacitance seen at the input terminals of the differential amplifier.

Abstract translation: 通过在每个输入晶体管的集电极和连接在另一个并联电流路径中的电阻器的端子之间连接正反馈路径来减小差分放大器的输入电容。 正反馈路径使得每个输入晶体管的集电极处的电压在与该输入晶体管的基极处的电压相同的方向上移动，从而降低在差分放大器的输入端子处看到的有效输入电容。

公开(公告)号：US20110157485A1

公开(公告)日：2011-06-30

申请号：US12844691

申请日：2010-07-27

Applicant: Alexander Fairgrieve ,  D. Stuart Smith

Inventor： Alexander Fairgrieve ,  D. Stuart Smith

IPC: H04N9/31 ,  H01S3/10

CPC classification number: H04N9/3173 ,  H04N9/312 ,  H04N9/3155

Abstract: Systems, methods and devices provide for fast and power efficient transfer of three color data words (e.g., a M-bit red color word, a M bit green color word and a M-bit blue color word) per pixel from a controller to a laser diode driver (LDD). First and second transfer words are produced based on the three color data words. The first transfer word is transferred from the controller to the LDD and stored at LDD in response to a low-to-high portion of a cycle of a data transfer clock, and the second transfer word is transferred and stored in response to a high-to-low portion of a cycle of the data transfer clock. The first, second and third color data words are reproduced by the LDD in dependence on the first and second received transfer words. First, second and third DACs of the LDD are driven with the first color data word, the second color data word, and the third color data word. Three light sources (e.g., red, green and blue laser diodes or LEDs) are driven with output currents of the DACs.

Abstract translation: 系统，方法和装置提供从控制器到每个像素的三色数据字（例如，M位红色字，M位绿色字和M位蓝色字）的快速和功率有效传输。 激光二极管驱动器（LDD）。 基于三色数据字产生第一和第二传送字。 第一传送字从控制器传送到LDD，并且响应于数据传输时钟的周期的低到高部分而存储在LDD处，并且响应于高速数据传送字符而传送和存储第二传送字， 数据传输时钟周期的低位部分。 第一，第二和第三颜色数据字由LDD根据第一和第二接收的传送字再现。 首先，利用第一颜色数据字，第二颜色数据字和第三颜色数据字来驱动LDD的第二和第三DAC。 三个光源（例如，红，绿和蓝激光二极管或LED）由DAC的输出电流驱动。

公开(公告)号：US07492686B2

公开(公告)日：2009-02-17

申请号：US11233193

申请日：2005-09-22

Applicant: Miguel Gabino Perez ,  Alexander Fairgrieve ,  Akihiro Asada

Inventor： Miguel Gabino Perez ,  Alexander Fairgrieve ,  Akihiro Asada

IPC: G11B5/09

CPC classification number: G11B7/00456 ,  G11B2007/0006

Abstract: Embodiments of the present invention relate to systems and methods for providing flexible multipulse strategies. In specific embodiments, a plurality of multipulse location registers are dedicated to storing multipulse location information. Each of a plurality of different mark-lengths that can result in at least one multipulse is mapped to one or more bit location within the multipulse location registers, such that a unique multipulse execution strategy can be defined for each of the plurality of different mark-lengths. Each bit location within the multipulse location registers can contain a first type of bit or a second type of bit. The first type of bit is used to indicate where to execute a multipulse, and the second type of bit is used to indicate where to not execute a multipulse. This abstract is not intended to be a complete description of the various embodiments of the present invention.

Abstract translation: 本发明的实施例涉及用于提供灵活多脉冲策略的系统和方法。 在具体实施例中，多个多脉冲位置寄存器专用于存储多脉冲位置信息。 可以导致至少一个多脉冲的多个不同的标记长度中的每一个被映射到多脉冲位置寄存器内的一个或多个比特位置，使得可以为多个不同的标记位中的每一个定义唯一的多脉冲执行策略， 长度 多脉冲位置寄存器中的每个位位置可以包含第一类型的位或第二类型的位。 第一种类型的位用于指示执行多脉冲的位置，第二种类型的位用于指示不执行多脉冲的位置。 该摘要并不是对本发明的各种实施例的完整描述。

公开(公告)号：US06501317B2

公开(公告)日：2002-12-31

申请号：US09828398

申请日：2001-04-06

Applicant: Xijian Lin ,  Barry Harvey ,  Alexander Fairgrieve

Inventor： Xijian Lin ,  Barry Harvey ,  Alexander Fairgrieve

IPC: H03K522

CPC classification number: H03H11/265

Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current. A wide frequency tuning range of a ring oscillator using the delay circuit of FIG. 2 is provided because the operating frequency for a ring oscillator will be directly proportional to the tail current through transistor 101.

Abstract translation: 提供了一种用于锁相环（PLL）的环形振荡器的延迟电路。 延迟电路包括NMOS晶体管102和103的差分对，NMOS晶体管101为差分对提供尾电流。 互补NMOS和PMOS负载晶体管104,106和105,107为差分晶体管102和103提供负载。晶体管111-114和121-122与放大器130一起为延迟器提供偏置。 放大器130具有设置为VDD-VCLAMP的非反相输入。 根据配置，在延迟器件的输出VOUT +和VOUT-上提供从VDD到VDD-VCLAMP的恒定输出电压摆幅，与用于设置尾部电流的控制电压VCTL无关。 NMOS负载晶体管104与图3中的PMOS晶体管4相反。 1，不影响栅极寄生电容，能够在不消耗更多电源电流的情况下实现高运行速度。 使用图1的延迟电路的环形振荡器的宽频率调谐范围。 提供了图2，因为环形振荡器的工作频率将与通过晶体管101的尾流成正比。

公开(公告)号：US20060182159A1

公开(公告)日：2006-08-17

申请号：US11399976

申请日：2006-04-07

Applicant: Alexander Fairgrieve ,  D. Smith ,  Theodore Rees ,  Bill Tang

Inventor： Alexander Fairgrieve ,  D. Smith ,  Theodore Rees ,  Bill Tang

IPC: H01S3/00 ,  H01S3/13

CPC classification number: G11B7/1263 ,  H01S5/042 ,  H01S5/0683

Abstract: Methods and system are provided for automatic power control of a laser diode, e.g., in a laser driver. In accordance with an embodiment of the present invention, a power controller includes a detector circuit adapted to detect the output of the laser diode and to produce a measured output therefrom. A comparator compares a desired output to the measured output, and produces an error signal therefrom. The error signal is provided to an integrator circuit that produces an integrated error signal. At least one digital-to-analog converter (DAC) uses the integrated error signal to produce a current drive signal that drives the laser diode.

公开(公告)号：US6031424A

公开(公告)日：2000-02-29

申请号：US150788

申请日：1998-09-10

Applicant: Alexander Fairgrieve

Inventor： Alexander Fairgrieve

IPC: H03F3/45 ,  H01H85/143

CPC classification number: H03F3/45085 ,  H03F2203/45352 ,  H03F2203/45584 ,  H03F2203/45641 ,  H03F2203/45648 ,  H03F2203/45696

Abstract: The present invention is a differential amplifier with circuitry to eliminate the effect of transistor impedance other than an actual load impedance on voltage gain. The circuitry includes a pair of transistors 400 and 402, each with a base connected to a respective input of the differential amplifier along with a similar base connection of a respective one of transistors 100 and 102, and an emitter connected to a current source 404. A collector of transistor 400 is connected through transistor 410 to the emitter of a current sink transistor 306, while the collector of transistor 402 is connected through transistor 412 to the emitter of a current sink transistor 308. Operational amplifiers (opamps) 420 and 422 serve as voltage followers to connect the collector of transistor 100 to the base of transistor 412, and the collector of transistor 102 to the base of transistor 410. An inverting input of the opamps 420 and 422 are connected to the emitter of transistors 410 and 412 to eliminate the effect of a emitter to base voltage drop in transistors 410 and 412. With such components, loading at the outputs V.sub.OUT and V.sub.OUTB is substantially limited to the actual load provided by transistors 306 and 308 and resistors 316 and 318.

Abstract translation: 本发明是一种差分放大器，其具有消除除实际负载阻抗之外的晶体管阻抗对电压增益的影响的电路。 该电路包括一对晶体管400和402，每个晶体管400和402各自具有连接到差分放大器的相应输入端的基极以及晶体管100和102的相应基极连接以及连接到电流源404的发射极。 晶体管400的集电极通过晶体管410连接到电流宿晶体管306的发射极，而晶体管402的集电极通过晶体管412连接到电流宿晶体管308的发射极。运算放大器（运算放大器）420和422 作为电压跟随器将晶体管100的集电极连接到晶体管412的基极，晶体管102的集电极连接到晶体管410的基极。运算放大器420和422的反相输入端连接到晶体管410和412的发射极， 消除了发射极对晶体管410和412中的基极电压降的影响。通过这样的部件，输出端VOUT和VOUTB的负载基本上限于 由晶体管306和308以及电阻器316和318提供的实际负载。