公开(公告)号：US20080081450A1

公开(公告)日：2008-04-03

申请号：US11752875

申请日：2007-05-23

申请人： Byoung Ki LEE

发明人： Byoung Ki LEE

IPC分类号： H01L21/3205

CPC分类号： H01L27/11573 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： In a method of manufacturing an SONOS type flash memory device, a first oxide layer and a buffer poly layer are formed over a surface of a semiconductor except for a memory cell region of a cell region. A second oxide layer, a nitride layer and a third oxide layer are formed. The poly buffer layer is exposed by etching specific regions in a peri region and in a DSL/SSL region of the cell region. A conductive layer is formed to electrically connect to the poly buffer layer. The third oxide layer, the nitride layer and the second nitride layer are selectively etched to form a gate of the memory cell region of the cell region. The buffer poly layer is selectively etched to form a gate in the DSL/SSL region of the cell region and a gate in the peri region.

摘要翻译： 在制造SONOS型闪速存储器件的方法中，除了单元区域的存储单元区域之外，在半导体的表面上形成第一氧化物层和缓冲多晶硅层。 形成第二氧化物层，氮化物层和第三氧化物层。 多缓冲层通过蚀刻细胞区域的周边区域和DSL / SSL区域中的特定区域而暴露。 形成导电层以电连接到多缓冲层。 选择性地蚀刻第三氧化物层，氮化物层和第二氮化物层以形成电池区域的存储单元区域的栅极。 选择性地蚀刻缓冲多晶硅层以在单元区域的DSL / SSL区域中形成栅极，并在周边区域形成栅极。

公开(公告)号：US20080081415A1

公开(公告)日：2008-04-03

申请号：US11747453

申请日：2007-05-11

申请人： Byoung-Ki Lee

发明人： Byoung-Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： A method of manufacturing a flash memory device. According to a method of manufacturing a flash memory device, since it comprises the steps of providing a semiconductor substrate including a cell region and a peripheral circuit region, forming a first oxide film and a nitride film subsequently over the semiconductor of the cell region, and forming the first oxide film, a buffer poly film and the nitride film over the semiconductor of the peripheral circuit region, forming a device isolation film by performing a process of the Self Align Shallow Trench Isolation (STI) over the semiconductor substrate including the first oxide film, the buffer poly film and the nitride film, forming a second oxide film and a control gate film over the whole structure including the device isolation film, and performing a gate pattering process as to the whole structure using a gate mask pattern; the nitride films storing charges are insulated on the respective gate to prevent a current leakage and a thinning phenomenon that may occur on a gate oxide film.

摘要翻译： 一种制造闪速存储器件的方法。 根据制造闪速存储器件的方法，由于它包括提供包括单元区域和外围电路区域的半导体衬底的步骤，随后在单元区域的半导体上形成第一氧化物膜和氮化物膜，以及 在外围电路区域的半导体上形成第一氧化膜，缓冲多晶硅膜和氮化物膜，通过在包括第一氧化物的半导体衬底上进行自对准浅沟槽隔离（STI）的工艺来形成器件隔离膜 膜，缓冲多晶膜和氮化物膜，在包括器件隔离膜的整个结构上形成第二氧化物膜和控制栅极膜，并且使用栅极掩模图案对整个结构进行栅极图案化处理; 存储电荷的氮化物膜在各个栅极上被绝缘，以防止在栅极氧化物膜上可能发生的电流泄漏和薄化现象。

公开(公告)号：US06987046B2

公开(公告)日：2006-01-17

申请号：US10882451

申请日：2004-06-30

申请人： In Kwon Yang ,  Byoung Ki Lee ,  Jung Woong Lee

发明人： In Kwon Yang ,  Byoung Ki Lee ,  Jung Woong Lee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/11521 ,  H01L21/32139 ,  H01L27/115

摘要： The present invention discloses a method for manufacturing a flash memory device including the steps of: sequentially forming a first polysilicon film for a floating gate electrode, a first oxide film, a polysilicon film for a hard mask and a second oxide film on a semiconductor substrate; etching and patterning the second oxide film and the polysilicon film for the hard mask, by forming photoresist patterns on a predetermined region of the second oxide film, and removing the photoresist patterns; forming spacers on the sidewalls of the polysilicon film for the hard mask, by forming and etching a polysilicon film for forming spacers on the whole surface of the resulting structure; removing the exposed first oxide film and a predetermined thickness of second oxide film formed on the patterned polysilicon film for the hard mask; forming floating gate electrode patterns by performing first and second etching processes by using the patterned polysilicon film for the hard mask and the spacers as an etch mask; performing a cleaning process on the whole surface of the resulting structure, and removing the residual second oxide film at the same time; and forming control gate electrode patterns, by sequentially forming and patterning an ONO film, a second polysilicon film for a control gate electrode, a metal silicide film and a hard mask on the resulting structure on which the floating gate electrode patterns have been formed.

摘要翻译： 本发明公开了一种闪速存储器件的制造方法，包括以下步骤：顺序地形成用于浮置栅极的第一多晶硅膜，第一氧化膜，用于硬掩模的多晶硅膜和半导体衬底上的第二氧化物膜 ; 通过在第二氧化膜的预定区域上形成光致抗蚀剂图案，去除光致抗蚀剂图案，蚀刻和图案化第二氧化物膜和用于硬掩模的多晶硅膜; 在用于硬掩模的多晶硅膜的侧壁上形成间隔物，通过在所得结构的整个表面上形成和蚀刻用于形成间隔物的多晶硅膜; 去除暴露的第一氧化物膜和形成在用于硬掩模的图案化多晶硅膜上的预定厚度的第二氧化膜; 通过使用用于硬掩模的图案化多晶硅膜和间隔物作为蚀刻掩模，通过执行第一和第二蚀刻工艺来形成浮栅电极图案; 在所得结构的整个表面上进行清洁处理，同时去除残留的第二氧化膜; 以及通过在其上形成有浮栅电极图案的所得结构上顺序地形成和图案化ONO膜，用于控制栅电极的第二多晶硅膜，金属硅化物膜和硬掩模来形成控制栅电极图案。

公开(公告)号：US06758898B2

公开(公告)日：2004-07-06

申请号：US10163526

申请日：2002-06-07

申请人： Ho-Yong Lee ,  Jao-Suk Kim ,  Jong-Bong Lee ,  Tae-Moo Hur ,  Doe-Yeon Kim ,  Nong-Moon Hwang ,  Byoung-Ki Lee ,  Sung-Yoon Chung ,  Suk-Joong L. Kang

发明人： Ho-Yong Lee ,  Jao-Suk Kim ,  Jong-Bong Lee ,  Tae-Moo Hur ,  Doe-Yeon Kim ,  Nong-Moon Hwang ,  Byoung-Ki Lee ,  Sung-Yoon Chung ,  Suk-Joong L. Kang

IPC分类号： C30B102

CPC分类号： C30B11/00 ,  C30B29/32

摘要： The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1−x)(TiyN1−y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has the advantage of providing an effective low cost in manufacturing process for single crystals by using a conventional heat-treatment process without the need of special equipment. The method for growing single crystals of barium titanate and barium titanate solid solutions according to this invention is also applicable to other material systems showing abnormal grain growth behavior.

摘要翻译： 本发明涉及一种生长钛酸钡[BaTiO3]和钛酸钡固溶体[（BaxM1-x）（TiyN1-y）O3]单晶的方法。 本发明涉及一种用于生长钛酸钡或钛酸钡固体溶液的单晶的方法，其显示出主要和次要的异常晶粒生长，其温度高于液体形成温度，其特征在于包括少量次级异常晶粒继续的步骤 在略低于次生异常晶粒生长开始发生的临界温度的温度下生长。 根据本发明的用于生长钛酸钡或钛酸钡固溶体的单晶的方法具有通过使用常规热处理工艺而不需要特殊设备来提供单晶制造工艺的有效低成本的优点。 根据本发明的用于生长钛酸钡和钛酸钡固溶体的单晶的方法也适用于显示异常晶粒生长行为的其它材料体系。

公开(公告)号：US20080003744A1

公开(公告)日：2008-01-03

申请号：US11618714

申请日：2006-12-29

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a non-volatile memory device includes forming first and second isolation structures in a substrate. A tunnel dielectric layer, a first conductive layer, a first insulating layer, and a second insulating layer are provided between the first and second isolation structures. The first and second insulating layers are removed to expose the first conductive layer. First and second vertical extensions are formed on the first conductive layer to form a U-shape structure. Upper portions of the first and second isolation structures are removed to define second gate trenches, so that each vertical extension has first and second sides exposed. A dielectric layer and a second conductive layer are formed to form a gate structure comprising the first conductive layer, the dielectric layer, and the second conductive layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在衬底中形成第一和第二隔离结构。 隧道介电层，第一导电层，第一绝缘层和第二绝缘层设置在第一和第二隔离结构之间。 去除第一和第二绝缘层以露出第一导电层。 在第一导电层上形成第一和第二垂直延伸部以形成U形结构。 去除第一和第二隔离结构的上部以限定第二栅极沟槽，使得每个垂直延伸部具有暴露的第一和第二侧面。 形成电介质层和第二导电层以形成包括第一导电层，电介质层和第二导电层的栅极结构。

公开(公告)号：US06482259B1

公开(公告)日：2002-11-19

申请号：US09646610

申请日：2001-02-20

申请人： Ho-Yong Lee ,  Jae-Suk Kim ,  Jong-Hong Lee ,  Tae-Moo Hur ,  Doe-Yeon Kim ,  Nong-Moon Hwang ,  Byoung-Ki Lee ,  Sung-Yoon Chung ,  Suk-Joong L. Kang

发明人： Ho-Yong Lee ,  Jae-Suk Kim ,  Jong-Hong Lee ,  Tae-Moo Hur ,  Doe-Yeon Kim ,  Nong-Moon Hwang ,  Byoung-Ki Lee ,  Sung-Yoon Chung ,  Suk-Joong L. Kang

IPC分类号： C30B110

CPC分类号： C30B11/00 ,  C30B29/32

摘要： The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1-x)(TiyN1-y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has an advantage to provide an effective low cost in manufacturing process for single crystals by using usual heat-treatment process without special equipments. The method for growing single crystals of barium titanate and barium titanate solid solutions according to this invention can be also applicable to other material systems showing abnormal grain growth behavior.

摘要翻译： 本发明涉及一种生长钛酸钡[BaTiO3]和钛酸钡固溶体[（BaxM1-x）（TiyN1-y）O3]单晶的方法。 本发明涉及一种用于生长钛酸钡或钛酸钡固体溶液的单晶的方法，其显示出主要和次要的异常晶粒生长，其温度高于液体形成温度，其特征在于包括少量次级异常晶粒继续的步骤 在略低于次生异常晶粒生长开始发生的临界温度的温度下生长。 根据本发明的用于生长钛酸钡或钛酸钡固溶体单晶的方法具有通过使用通常的热处理工艺而无需特殊设备来提供单晶制造工艺中有效的低成本的优点。 根据本发明的用于生长钛酸钡和钛酸钡固溶体的单晶的方法也可以应用于显示异常晶粒生长行为的其它材料体系。

公开(公告)号：US20100288418A1

公开(公告)日：2010-11-18

申请号：US12841347

申请日：2010-07-22

申请人： JAE SUK YANG ,  HYEON CHUL LIM ,  BYOUNG KI LEE ,  YONG SUP LEE ,  YONG HYUN KIM ,  YONG SUL SONG ,  SANG KYUN KWON ,  BEOM JIN KIM

发明人： JAE SUK YANG ,  HYEON CHUL LIM ,  BYOUNG KI LEE ,  YONG SUP LEE ,  YONG HYUN KIM ,  YONG SUL SONG ,  SANG KYUN KWON ,  BEOM JIN KIM

IPC分类号： B32B37/02 ,  B22F7/04 ,  B22D23/00 ,  B32B37/16 ,  B32B37/24

CPC分类号： G06K19/07771 ,  H01Q1/22 ,  H01Q17/00

摘要： Provided are a magnetic sheet for use in a radio frequency identification (RFID) antenna, an RFID antenna including the magnetic sheet, and a method of manufacturing the magnetic sheet, in which the magnetic sheet includes an amorphous alloy selected from the group consisting of Fe—Si—B, Fe—Si—B—Cu—Nb, Fe—Zr—B and Co—Fe—Si—B. The magnetic sheet is made by laminating amorphous alloy ribbons made of an amorphous alloy between magnetic sheet layers formed of alloy powder including at least one amorphous alloy and then compression-molding the amorphous alloy ribbons, to thereby control microcrack of the amorphous alloy ribbons and enhance characteristic of an end-product. The magnetic sheet is also thin, and has an excellent magnetic permeability, and a simple manufacturing process.

摘要翻译： 提供了一种用于射频识别（RFID）天线的磁性片，包括该磁性片的RFID天线，以及制造该磁性片的方法，其中该磁性片包括选自Fe -Si-B，Fe-Si-B-Cu-Nb，Fe-Zr-B和Co-Fe-Si-B。 该磁性片是通过在由包括至少一种非晶态合金的合金粉末形成的磁性层之间层叠由非晶合金制成的非晶合金带，然后压制非晶态合金带的方法制成的，从而控制非晶合金带的微裂纹并增强 最终产品的特点。 磁性薄片也薄，并且具有优异的导磁率和简单的制造工艺。

公开(公告)号：US20080003743A1

公开(公告)日：2008-01-03

申请号：US11605130

申请日：2006-11-28

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a NAND flash memory device, wherein isolation layers are formed in a semiconductor substrate, and an upper side of each of the isolation layers is made to have a negative profile. A polysilicon layer is formed on the entire surface. At this time, a seam is formed within the polysilicon layer due to the negative profile. A post annealing process is performed in order to make the seam to a void. Accordingly, an electrical interference phenomenon between cells can be reduced and a threshold voltage (Vt) shift value can be lowered.

摘要翻译： 一种制造NAND闪存器件的方法，其中在半导体衬底中形成隔离层，并且使每个隔离层的上侧具有负轮廓。 在整个表面上形成多晶硅层。 此时，由于阴性轮廓，在多晶硅层内形成接缝。 进行后退火处理以使接缝成为空隙。 因此，可以减小电池之间的电气干扰现象，并且可以降低阈值电压（Vt）偏移值。

公开(公告)号：US07026213B1

公开(公告)日：2006-04-11

申请号：US11166484

申请日：2005-06-24

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11568

摘要： The present invention relates to a method of fabricating a flash memory device. According to the present invention, an oxide film is deposited and etched to form trenches, the trenches are filled with a metal film, and the metal film undergoes CMP to form bit lines. In this case, an etch stop layer of the trench etch process, a CMP stop layer of a CMP process and a wet barrier on the sides of the trenches are formed using a thermally treated SiON film having an etch rate lower than that of a wet chemical. As such, since a thickness and width of bit lines can be made uniform, bit line resistance and capacitance can be maintained constantly.

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 根据本发明，沉积并蚀刻氧化膜以形成沟槽，用金属膜填充沟槽，并且金属膜经历CMP以形成位线。 在这种情况下，使用热处理的SiON膜，其蚀刻速率低于湿法蚀刻速率，形成沟槽蚀刻工艺的蚀刻停止层，CMP工艺的CMP停止层和沟槽侧面上的湿势 化学品。 因此，由于可以使位线的厚度和宽度均匀，可以恒定地保持位线电阻和电容。

公开(公告)号：US06884682B2

公开(公告)日：2005-04-26

申请号：US10734533

申请日：2003-12-12

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11541

摘要： The present invention relates to a method of manufacturing a flash memory device. In a flash memory device formed by applying a self-align shallow trench isolation (SA-STI) scheme, a polishing process and a process for removing a nitride film are performed after oxide materials are buried in isolation trenches. Then, oxide films with an excellent planarization are formed, a first etching process is performed to selectively remove the oxide films in a low voltage transistor/cell area to a certain thickness, a second etching process is performed to remove the oxide films in a high voltage transistor area and the low voltage transistor/cell area until a poly-silicon layer for a floating gate is exposed. Therefore, protruding portions of element isolation films in the high voltage transistor area and the low voltage transistor/cell area are etched away to a certain thickness during the first and second etching processes so that a difference in EFH's between these areas can be reduced.

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 在通过施加自对准浅沟槽隔离（SA-STI）方案形成的快闪存储器件中，在氧化物材料埋入隔离沟槽中之后，进行抛光工艺和去除氮化物膜的工艺。 然后，形成具有优异平坦化的氧化物膜，进行第一蚀刻工艺以选择性地将低电压晶体管/电池区域中的氧化物膜去除到一定厚度，进行第二蚀刻工艺以将氧化膜去除 电压晶体管区域和低电压晶体管/单元面积直到露出用于浮动栅极的多晶硅层。 因此，在第一和第二蚀刻工艺期间，高压晶体管区域和低压晶体管/单元区域中的元件隔离膜的突出部分被蚀刻掉到一定厚度，从而可以减小这些区域之间的EFH差。