公开(公告)号：US6117732A

公开(公告)日：2000-09-12

申请号：US193671

申请日：1998-11-17

Applicant: Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

Inventor： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825

Abstract: A method for fabricating a single polysilicon, non-volatile memory device, has been developed. The method features the use of a metal structure, comprised to contact an underlying control gate region, located in the semiconductor structure, in addition to providing the upper electrode, for a capacitor structure. The capacitor structure, in addition to the metal structure used as the upper electrode, is also comprised of an underlying capacitor dielectric layer, and an underlying polysilicon floating gate structure, used as the lower electrode of the capacitor structure. The creation of the capacitor structure results in performance increases realized via the additional control gate coupling capacitance, obtained via the novel configuration described in this invention.

Abstract translation: 已经开发了用于制造单个多晶硅，非易失性存储器件的方法。 该方法的特征在于，除了为电容器结构提供上电极之外，金属结构的使用还包括接触位于半导体结构中的底层控制栅极区域。 除了用作上电极的金属结构之外，电容器结构还包括用作电容器结构的下电极的下层电容器介电层和下面的多晶硅浮栅结构。 电容器结构的产生导致通过经由本发明中描述的新颖结构获得的附加控制栅极耦合电容实现的性能提高。

公开(公告)号：US06753569B2

公开(公告)日：2004-06-22

申请号：US10029622

申请日：2001-12-31

Applicant: Yai-Fen Lin ,  Chang Song Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh

Inventor： Yai-Fen Lin ,  Chang Song Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh

IPC: H01L2976

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.

Abstract translation: 提供了一种用于形成具有浅沟槽隔离的分离栅极闪存单元的方法，而不会在包围第一多晶硅层的沟槽的边缘附近侵入“微笑”间隙。 这通过在沟槽的内壁上形成两个共形层来实现。 覆盖第一保形氧化物层的非常薄的氮化物层在第一多晶硅层的氧化期间提供必要的保护，以防止在制造超大规模集成电路时通常遇到的“微笑”效应。