公开(公告)号：US07464357B2

公开(公告)日：2008-12-09

申请号：US11341481

申请日：2006-01-30

Applicant: An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

Inventor： An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

IPC: G06F17/50

CPC classification number: G01R31/318538 ,  G01R31/31855

Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

Abstract translation: 用于定位故障过程层的集成电路。 电路具有设置在其中的扫描链的基板，其具有连接以形成串联链的扫描单元。 每个连接根据由分配的路由层的设计规则提供的最小维度的布局约束形成。 由于分配的路由层中的连接被限制到最小限度，扫描链很容易受到与分配的路由层相关的进程变化的影响。 扫描链使得更容易定位导致扫描链的低产率的过程。

公开(公告)号：US20060123375A1

公开(公告)日：2006-06-08

申请号：US11341481

申请日：2006-01-30

Applicant: An-Ru Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

Inventor： An-Ru Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

IPC: G06F17/50 ,  G01R31/28

CPC classification number: G01R31/318538 ,  G01R31/31855

Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

公开(公告)号：US6110782A

公开(公告)日：2000-08-29

申请号：US195651

申请日：1998-11-19

Applicant: Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chon Ho ,  Chang-Song Lin ,  Di-Son Kwo

Inventor： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chon Ho ,  Chang-Song Lin ,  Di-Son Kwo

IPC: H01L21/8234 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L21/823462 ,  H01L27/11541

Abstract: A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low voltage device area from a high voltage device area. A gate oxide layer is grown in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. A first photomask is formed over a portion of the high voltage device area wherein the first photomask also completely covers the low voltage device area. The polysilicon layer is etched away where it is not covered by the photomask to form a high voltage device. Ions are implanted to form lightly doped source and drain regions within the semiconductor substrate adjacent to the high voltage device wherein the first photomask protects the polysilicon layer in the low voltage device area from the ions. The first photomask is removed. A second photomask is formed over a portion of the low voltage device area where a gate electrode is to be formed wherein the second photomask also completely covers the high voltage device area. The polysilicon layer not covered by the second photomask is etched away to form the gate electrode. The second photomask is removed. The low voltage and high voltage area devices are silicided and the fabrication of the integrated circuit device is completed.

Abstract translation: 描述了在单个晶片上制造高电压和低压器件中的自对准硅化物和高电压器件工艺的集成方法。 在半导体衬底上形成隔离区域，该半导体衬底围绕低电压器件区域和高电压器件区域电隔离。 在器件区域中生长栅极氧化物层。 沉积覆盖栅极氧化物层和隔离区的多晶硅层。 第一光掩模形成在高电压器件区域的一部分上，其中第一光掩模也完全覆盖低电压器件区域。 多晶硅层被蚀刻掉，其未被光掩模覆盖以形成高压器件。 植入离子以在与高压器件相邻的半导体衬底内形成轻掺杂的源极和漏极区，其中第一光掩模保护低电压器件区域中的多晶硅层与离子。 第一个光掩模被删除。 第二光掩模形成在要形成栅电极的低电压器件区域的一部分上，其中第二光掩模也完全覆盖高电压器件区域。 蚀刻掉未被第二光掩模覆盖的多晶硅层以形成栅电极。 第二个光掩模被删除。 低电压和高电压区域的器件被硅化，并且完成了集成电路器件的制造。

公开(公告)号：US06358796B1

公开(公告)日：2002-03-19

申请号：US09292360

申请日：1999-04-15

Applicant: Yai-Fen Lin ,  Chang-Song Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh

Inventor： Yai-Fen Lin ,  Chang-Song Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.

公开(公告)号：US5747382A

公开(公告)日：1998-05-05

申请号：US719232

申请日：1996-09-24

Applicant: Yung-Sheng Huang ,  Long-Sheng Yeou ,  Ji-Chung Huang ,  Chang-Song Lin

Inventor： Yung-Sheng Huang ,  Long-Sheng Yeou ,  Ji-Chung Huang ,  Chang-Song Lin

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/316

CPC classification number: H01L21/76819 ,  H01L21/31053

Abstract: A novel method is presented to form and planarize an inter-metal-dielectric(IMD) layer of an integrated circuit with two or more levels of interconnection metallurgy. The method utilizes chemical-mechanical-polishing(CMP) followed by reactive-ion-etching(RIE) to first planarize and then etch back a deposited IMD layer. Metal line spacings of less than 1.5 microns produce voids in the IMD even when spin-on-glass(SOG) is used to partially fill the spaces prior to IMD deposition. These voids, which contain organic residues and debris, can produce eruptions of material during several subsequent processing steps. The method of this invention attenuates and de-activates these voids, rendering them completely benign. Since CMP is only used to achieve a planar surface, risks of CMP damage to alignment marks and other features are also reduced.

Abstract translation: 提出了一种新颖的方法来形成和平面化具有两层或多层互连冶金的集成电路的金属间电介质（IMD）层。 该方法利用化学机械抛光（CMP），然后进行反应离子蚀刻（RIE）来首先平坦化，然后回蚀沉积的IMD层。 即使使用旋涂玻璃（SOG）在IMD沉积之前部分填充空间，小于1.5微米的金属线间距也会在IMD中产生空隙。 这些含有有机残留物和碎屑的空隙在几个后续处理步骤中可能会产生材料的喷发。 本发明的方法减弱和去激活这些空隙，使它们完全良性。 由于CMP仅用于实现平面，因此CMP对对准标记和其它特征的损害也将降低。

公开(公告)号：US6090668A

公开(公告)日：2000-07-18

申请号：US248725

申请日：1999-02-11

Applicant: Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

Inventor： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

IPC: H01L21/28 ,  H01L21/8247 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

Abstract: A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Abstract translation: 提供了一种用于形成具有尖锐多边尖端的分裂栅极闪存单元的方法，其基本上改善了单元的擦除速度。 形成多边形，而不需要多晶硅浮动栅极的常规氧化。 相反，使用高压配方蚀刻多晶硅层，从而形成具有倾斜轮廓的凹陷到多晶硅层中。 凹部填充有顶部氧化物，其又用作蚀刻多晶硅年份未被顶部氧化物层保护的那些部分的硬掩模。 由凹陷的倾斜壁形成的多晶硅层的边缘形成本发明的尖锐的多边形尖端。 锋利的尖端不会经历由常规聚氧化过程引起的损坏，因此为分离式闪存单元提供增强的擦除速度。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US5872042A

公开(公告)日：1999-02-16

申请号：US701363

申请日：1996-08-22

Applicant: Shun-Liang Hsu ,  Syun-Ming Jang ,  Chang-Song Lin

Inventor： Shun-Liang Hsu ,  Syun-Ming Jang ,  Chang-Song Lin

IPC: H01L23/544 ,  H01L21/465

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

Abstract: The contact or via hole etch pattern photomask used in fabrication of integrated circuits is modified to provide a series of grooves or trenches to be etched in the silicon oxide layer simultaneously with the contact or via holes. These trenches, after deposition and planarization of tungsten metal layer, afford regenerated alignment marks with sharply-defined edges even after deposition of a second conductive layer.

Abstract translation: 在集成电路的制造中使用的接触或通孔蚀刻图案光掩模被修改以提供与该接触或通孔同时蚀刻在氧化硅层中的一系列凹槽或沟槽。 在钨金属层的沉积和平坦化之后，即使在沉积第二导电层之后，这些沟槽也提供了具有锐利界定边缘的再生对准标记。

公开(公告)号：US07036099B2

公开(公告)日：2006-04-25

申请号：US10626634

申请日：2003-07-25

Applicant: An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

Inventor： An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

IPC: G06F17/50

CPC classification number: G01R31/318538 ,  G01R31/31855

Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

Abstract translation: 用于定位故障过程层的集成电路。 电路具有设置在其中的扫描链的基板，其具有连接以形成串联链的扫描单元。 每个连接根据由分配的路由层的设计规则提供的最小维度的布局约束形成。 由于分配的路由层中的连接被限制到最小限度，扫描链很容易受到与分配的路由层相关的进程变化的影响。 扫描链使得更容易定位导致扫描链的低产率的过程。

公开(公告)号：US20050022142A1

公开(公告)日：2005-01-27

申请号：US10626634

申请日：2003-07-25

Applicant: An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

Inventor： An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

IPC: G01R31/3185 ,  G06F17/50 ,  G06F9/45 ,  H03K19/00

CPC classification number: G01R31/318538 ,  G01R31/31855

Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

Abstract translation: 用于定位故障过程层的集成电路。 电路具有设置在其中的扫描链的基板，其具有连接以形成串联链的扫描单元。 每个连接根据由分配的路由层的设计规则提供的最小维度的布局约束形成。 由于分配的路由层中的连接被限制到最小限度，扫描链很容易受到与分配的路由层相关的进程变化的影响。 扫描链使得更容易定位导致扫描链的低产率的过程。

公开(公告)号：US06417046B1

公开(公告)日：2002-07-09

申请号：US09563834

申请日：2000-05-05

Applicant: Ming-Chou Ho ,  Wen-Ting Chu ,  Chang Song Lin ,  Chuan-Li Chang ,  Hsin-Ming Chen ,  Di-Son Kuo

Inventor： Ming-Chou Ho ,  Wen-Ting Chu ,  Chang Song Lin ,  Chuan-Li Chang ,  Hsin-Ming Chen ,  Di-Son Kuo

IPC: H01L21336

CPC classification number: H01L21/28211 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/6659

Abstract: A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.