公开(公告)号：US5846865A

公开(公告)日：1998-12-08

申请号：US745468

申请日：1996-11-12

Applicant: Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

Inventor： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

IPC: H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC classification number: H01L27/11253 ,  H01L27/112 ,  Y10S148/02

Abstract: A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions. Thereafter, a third polysilicon layer is formed over the second polysilicon layer and the insulating layers, and finally the third polysilicon layer is defined to form a gate for the integrated circuit device. Since the source/drain regions are made of tungsten metal, the spacing distance therebetween will not be changed when subjected to high-temperature conditions during subsequent process steps. The punch-through effect can thus be avoided.

Abstract translation: 一种制造平面单元掩膜ROM器件的方法，其具有在形成掩埋位线之后的随后步骤中加热的结果之后不会在相邻位线之间穿透的掩埋位线。 在该方法中，第一步是制备其上形成有栅氧化层的半导体衬底。 此后，在栅极氧化物层上形成第一多晶硅层，并在预定位置形成多个沟槽，其中这些沟槽延伸穿过栅极氧化物和第一多晶硅层并进入衬底至预定深度。 然后，用钨填充沟槽以形成多个源极/漏极区域。 然后在第一多晶硅层上形成第二多晶硅层，并且在每个源/漏区上形成绝缘层。 此后，在第二多晶硅层和绝缘层上形成第三多晶硅层，最后形成第三多晶硅层以形成用于集成电路器件的栅极。 由于源极/漏极区域由钨金属制成，因此在后续工艺步骤中经受高温条件时，它们之间的间隔距离将不会改变。 因此可以避免穿透效果。

公开(公告)号：US5668031A

公开(公告)日：1997-09-16

申请号：US658673

申请日：1996-06-04

Applicant: Chen-Chiu Hsue ,  Cheng-Hui Chung ,  Yi-Chung Sheng

Inventor： Chen-Chiu Hsue ,  Cheng-Hui Chung ,  Yi-Chung Sheng

IPC: H01L21/8246 ,  H01L27/112 ,  H01L21/70

CPC classification number: H01L27/11253 ,  H01L27/112

Abstract: A method of fabricating a high density flat mask read only memory. At first a plurality of trenches are formed in a surface of a silicon substrate at predetermined desired source-drain electrodes areas. A dielectric layer is formed on at least the surface of the trenches. A first polysilicon layer is formed over the dielectric layer and then portions of the first polysilicon layer are removed to leave a portion thereof on the bottom of each trench. Using the first polysilicon layer as an etch stop layer, the dielectric layer is etched. A second polysilicon layer then is formed on the surface of the silicon substrate, the first polysilicon layer and the dielectric layer, and then the the second polysilicon layer is etched back to the substrate surface to form the source-drain electrode areas, that is, the bit lines. On the surface of the bit lines and the silicon substrate, a gate oxide layer and a third polysilicon layer are formed sequentially. Finally, the gate oxide layer and the third polysilicon layer are defined to form gate electrodes, that is, word lines for the memory.

Abstract translation: 一种制造高密度平面掩模只读存储器的方法。 首先，在预定的期望的源极 - 漏极电极区域的硅衬底的表面中形成多个沟槽。 在沟槽的至少表面上形成介电层。 在电介质层上形成第一多晶硅层，然后去除第一多晶硅层的部分，以将其部分留在每个沟槽的底部。 使用第一多晶硅层作为蚀刻停止层，蚀刻介电层。 然后在硅衬底，第一多晶硅层和电介质层的表面上形成第二多晶硅层，然后将第二多晶硅层回蚀刻到衬底表面以形成源极 - 漏极电极区域，即， 位线。 在位线和硅衬底的表面上依次形成栅氧化层和第三多晶硅层。 最后，栅极氧化物层和第三多晶硅层被定义为形成栅电极，即用于存储器的字线。