公开(公告)号：US07206733B1

公开(公告)日：2007-04-17

申请号：US09975105

申请日：2001-10-10

申请人： Craig Nemecek

发明人： Craig Nemecek

IPC分类号： G06F9/455 ,  G06F13/00

CPC分类号： G06F11/3652 ,  G06F11/3656

摘要： A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.

摘要翻译： 主机与FPGA之间的多用途接口。 该接口使用符合IEEE 1284标准的EPP模式连接。 当主计算机初始化时，执行FPGA的复位以清除FPGA的配置存储器。 然后将接口的数据线用于将单向配置数据传送到FPGA。 数据由主计算机使用数据选通信号线对数据进行时钟输入到FPGA中。 当FPGA完全编程时，包括将符合IEEE 1284标准的EPP模式接口编程到FPGA中，数据线用于主计算机和配置的FPGA之间的双向通信，在此实施例中操作为虚拟微控制器。

公开(公告)号：US07185321B1

公开(公告)日：2007-02-27

申请号：US10113064

申请日：2002-03-29

申请人： Steve Roe ,  Matt Pleis ,  Craig Nemecek

发明人： Steve Roe ,  Matt Pleis ,  Craig Nemecek

IPC分类号： G06F9/44 ,  G06F11/00

CPC分类号： G06F11/3664 ,  G06F11/3636

摘要： Embodiments of the present invention effectuate a method and system for debugging a device such as a microcontroller in a distributed architectural scheme, where the device may operate at speeds much faster than the debugger program is run, with limited debugging resources physically incorporated into the device itself, and with relatively limited computational capacity, vis-à-vis the platform deploying the debugging software. The embodiments place relatively modest, uncomplicated demands on the debugger software, and the ICE may also be relatively simple. Further, debugging methods and systems according to these embodiments are flexible and adaptable to a variety of different devices that must undergo debugging, yet remain effective, simple, and inexpensive.

摘要翻译： 本发明的实施例实现了一种用于在分布式架构方案中调试诸如微控制器的设备的方法和系统，其中设备可以以比调试器程序运行的速度快得多的速度运行，其中有限的调试资源被物理地并入设备本身 相对于部署调试软件的平台，计算量相对有限。 这些实施例对调试器软件提出了相对适度的，简单的要求，并且ICE也可以相对简单。 此外，根据这些实施例的调试方法和系统是灵活的，并且适用于必须进行调试的各种不同的设备，但是保持有效，简单和便宜。

公开(公告)号：US07089175B1

公开(公告)日：2006-08-08

申请号：US10001568

申请日：2001-11-01

申请人： Craig Nemecek ,  Steve Roe

发明人： Craig Nemecek ,  Steve Roe

IPC分类号： G06F9/455

CPC分类号： G06F11/3652

摘要： A combined in-circuit emulation system and device programmer. A pod assembly used in an in-circuit emulation system has both a real microcontroller used in the In-Circuit Emulation and debugging process as well as a socket that accommodates a microcontroller to be programmed (a program microcontroller). Programming can be carried out over a single interface that is shared between the microcontroller and the program microcontroller and which is also used to provide communication between the real microcontroller and the In-Circuit Emulation system to carry out emulation functions. In order to assure that the emulation microcontroller does not interfere with the programming process for a microcontroller placed in a programming socket, a special sleep mode is implemented in the emulation microcontroller. This sleep mode is activated by a process that takes place at power on in which the a reset line is released with a specified data line held in a logic high state.

摘要翻译： 组合在线仿真系统和器件编程器。 在线仿真系统中使用的pod组件具有在线程仿真和调试过程中使用的真实微控制器以及容纳要编程的微控制器（程序微控制器）的插座。 可以通过在微控制器和程序微控制器之间共享的单个接口进行编程，并且还用于提供真实微控制器和在线仿真系统之间的通信，以执行仿真功能。 为了确保仿真微控制器不会干扰放置在编程插槽中的微控制器的编程过程，在仿真微控制器中实现特殊的睡眠模式。 这种睡眠模式由上电开始的过程激活，其中以指定的数据线保持在逻辑高状态来释放复位线。

公开(公告)号：US07035886B1

公开(公告)日：2006-04-25

申请号：US10109743

申请日：2002-03-28

申请人： Craig Nemecek ,  Steve Roe

发明人： Craig Nemecek ,  Steve Roe

IPC分类号： G06F15/00

CPC分类号： G01R31/318357 ,  G01R31/318516

摘要： A re-configurable combinational logic device. The device comprises combinational logic that inputs a number of signals and a memory array for storing data to define Boolean expressions for a number of states. The states have Boolean expressions of selected signals of the signals input to the combinational logic. The combinational logic is configurable, in response to the data, to select the signals as operands for said Boolean expression and to output a signal that is the result of the Boolean expression. The combinational logic is re-configurable, in response to further data from the memory array, to output a signal that is the result of additional Boolean expressions.

摘要翻译： 可重组的组合逻辑器件。 该设备包括输入多个信号的组合逻辑和用于存储数据的存储器阵列以定义多个状态的布尔表达式。 状态具有输入到组合逻辑的信号的选定信号的布尔表达式。 组合逻辑是可配置的，响应于数据，将信号选择为所述布尔表达式的操作数，并输出作为布尔表达式的结果的信号。 组合逻辑是可重新配置的，以响应来自存储器阵列的更多数据，输出作为附加布尔表达式的结果的信号。

公开(公告)号：US06922821B1

公开(公告)日：2005-07-26

申请号：US09998859

申请日：2001-11-15

申请人： Craig Nemecek

发明人： Craig Nemecek

IPC分类号： G06F9/44 ,  G06F11/26 ,  G06F17/50

CPC分类号： G06F11/261

摘要： Checking the consistency of a lock step process while debugging a microcontroller code is in progress. A method provides a production microcontroller to execute an instruction code and provides the result of the instruction code to an ICE. The ICE, independent from the production microcontroller and simultaneously, executes the same instruction code and produces a result. The ICE compares the result of its computation and the result received from the production microcontroller. The ICE issues a “lock step error” when the result of the comparison is a mismatch. A trace buffer residing in the host device provides the location of the line of code causing the mismatch. After identifying the line of code causing the mismatch the user debugs the erroneous line of code. The debugging process resumes on the next line of code in the microcontroller code under test.

摘要翻译： 正在调试微控制器代码时检查锁定步骤过程的一致性。 一种方法提供一种生产微控制器来执行指令代码并将指令代码的结果提供给ICE。 ICE独立于生产微控制器并同时执行相同的指令代码并产生结果。 ICE将其计算结果与从生产微控制器获得的结果进行比较。 当比较结果不匹配时，ICE会发出“锁定步骤错误”。 驻留在主机设备中的跟踪缓冲区提供导致不匹配的代码行的位置。 在识别导致不匹配的代码行之后，用户调试错误的代码行。 调试过程将在微控制器代码中的下一行代码中恢复测试。

公开(公告)号：US08103497B1

公开(公告)日：2012-01-24

申请号：US10113581

申请日：2002-03-28

申请人： Craig Nemecek ,  Steve Roe

发明人： Craig Nemecek ,  Steve Roe

IPC分类号： G06F9/455 ,  H03K17/693 ,  G01R31/00 ,  G06F13/28

CPC分类号： G06F11/261

摘要： A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.

摘要翻译： 用于监控事件的设备。 设备可以具有用于检测事件的可编程事件引擎和耦合到事件引擎的存储器阵列。 该阵列可以存储用于编程事件引擎以监视事件的数据。 该设备可以具有连接到事件引擎的外部引脚。 事件引擎可以监视外部引脚上的信号，以检测设备外部的事件。 或者，该装置可以响应于检测到一个事件而在外部引脚上输出信号。

公开(公告)号：US08103496B1

公开(公告)日：2012-01-24

申请号：US10001477

申请日：2001-11-01

申请人： Steve Roe ,  Craig Nemecek

发明人： Steve Roe ,  Craig Nemecek

IPC分类号： G06F9/455 ,  G06F11/36

CPC分类号： G06F11/3656 ,  G06F11/3652

摘要： A breakpoint control mechanism for an In-Circuit Emulation system. Break bits are assigned to each instruction address and stored in a lookup table within a base station containing a virtual microcontroller. As a program counter increments, a determination is made as to whether or not a break is to occur by reading the break bit from the lookup table. When a break is to occur, a breakpoint controller issues a break command over an interface to an actual microcontroller under test, thus freeing the microcontroller under test from having to include a look-up table on board for a breakpoint control or otherwise provide specifically for breakpoint control.

摘要翻译： 一种在线仿真系统的断点控制机制。 分配位被分配给每个指令地址并存储在包含虚拟微控制器的基站内的查找表中。 当程序计数器递增时，通过从查找表读取断点来确定是否发生中断。 当断点发生时，断点控制器通过接口连接到实际测试的微控制器，从而释放被测微控制器，不必在板上包含一个查找表来进行断点控制，或者专门为 断点控制。

公开(公告)号：US07765095B1

公开(公告)日：2010-07-27

申请号：US10002217

申请日：2001-11-01

申请人： Craig Nemecek

发明人： Craig Nemecek

IPC分类号： G06F9/455

CPC分类号： G06F11/3656

摘要： An In-Circuit Emulation system. A real microcontroller (device under test) operates in lock-step with a virtual microcontroller so that registers, memory locations and other debugged data can be retrieved from the virtual microcontroller without disrupting operation of a real microcontroller. When an I/O read instruction is carried out followed by a conditional jump instruction dependent upon the I/O read data, the virtual microcontroller does not have adequate time to compute the jump address after receipt of I/O read data from the real microcontroller. Thus, when this sequence of instructions is detected, the virtual microcontroller pre-calculates the jump address and makes the jump decision after receipt of the I/O read data from the real microcontroller.

摘要翻译： 在线仿真系统。 真正的微控制器（被测设备）与虚拟微控制器锁定工作，从而可以从虚拟微控制器检索寄存器，存储器位置和其他调试数据，而不会中断真实微控制器的操作。 当执行I / O读取指令后，依赖于I / O读取数据的条件跳转指令时，虚拟微控制器在从真实微控制器接收I / O读取数据之后没有足够的时间来计算跳转地址 。 因此，当检测到该指令序列时，虚拟微控制器预先计算跳转地址，并在从真实微控制器接收到I / O读取数据之后进行跳转决定。

公开(公告)号：US07526422B1

公开(公告)日：2009-04-28

申请号：US09992076

申请日：2001-11-13

申请人： Craig Nemecek

发明人： Craig Nemecek

IPC分类号： G06F9/455

CPC分类号： G06F17/5027 ,  G06F11/261 ,  G06F11/3632 ,  G06F11/3656

摘要： A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. A host device copies a partially copies a production microcontroller in an ICE (in-circuit emulation) to form a virtual microcontroller. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code for debugging purposes. The microcontroller residing on a test circuit includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. Software in the host device compares the content of the first memory and the content of the second memory for consistency. In case of a disparity between the content of the first memory and the content of the second memory, a user traces the execution of the code in a trace buffer residing in the ICE and debugs the faulty code accordingly.

摘要翻译： 一种用于在调试微控制器代码时检查锁步过程一致性的系统和方法。 主机设备复制部分复制ICE中的生产微控制器（在线仿真）以形成虚拟微控制器。 虚拟微控制器和微控制器同时独立运行一个微控制器代码进行调试。 驻留在测试电路上的微控制器包括第一存储器，驻留在ICE中的虚拟微控制器包括第二存储器。 当代码的执行停止时，主计算机将主机计算机存储器中的第一存储器的内容和第二存储器的内容复制。 主机中的软件比较第一存储器的内容和第二存储器的内容以保持一致。 在第一存储器的内容和第二存储器的内容之间的差异的情况下，用户跟踪驻留在ICE中的跟踪缓冲器中的代码的执行，并相应地调试故障代码。

公开(公告)号：US20070176903A1

公开(公告)日：2007-08-02

申请号：US11343402

申请日：2006-01-31

申请人： Jeffrey Dahlin ,  Craig Nemecek ,  Andrew Page

发明人： Jeffrey Dahlin ,  Craig Nemecek ,  Andrew Page

IPC分类号： G09G5/00 ,  G06F3/02

CPC分类号： G06F3/03547 ,  G06F3/04883 ,  H03K17/9622 ,  H03K2217/96058 ,  H03K2217/96066

摘要： A first touch is sensed at a first button on a capacitive touch sensor. A second button on the capacitive touch sensor is activated using one of a search-and-tap technique or a search-and-lift technique.

摘要翻译： 在电容式触摸传感器上的第一按钮处感测到第一触摸。 电容式触摸传感器上的第二个按钮使用搜索和抽头技术或搜索和提升技术之一进行激活。