公开(公告)号：US07184509B2

公开(公告)日：2007-02-27

申请号：US10619821

申请日：2003-07-14

Applicant: Geun-Hee Cho ,  Kyu-Hyoun Kim

Inventor： Geun-Hee Cho ,  Kyu-Hyoun Kim

IPC: H03D3/24 ,  H03L7/06

CPC classification number: H03L7/0814 ,  H03K5/13 ,  H03K5/1565 ,  H03L7/089

Abstract: A delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves the characteristics of a memory device is described. The delay locked loop circuit includes an additional loop for duty cycle correction as well as loops for controlling a rising edge and a falling edge of output signals. Thus, the delay locked loop circuit can internally correct the duty cycle without the use of a phase blender.

Abstract translation: 具有占空比校正器（DCC）的占空比校正器（DCC）的延迟锁定环路（DCC）具有宽范围的占空比校正，仅消耗少量功率，对工作频率的限制较少，并且提高了存储器件的特性 描述。 延迟锁定环电路包括用于占空比校正的附加回路以及用于控制输出信号的上升沿和下降沿的回路。 因此，延迟锁定环电路可以在不使用相位搅拌器的情况下内部校正占空比。

公开(公告)号：US20050105294A1

公开(公告)日：2005-05-19

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: G11C11/40 ,  F21V1/00 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。