公开(公告)号：US08418221B1

公开(公告)日：2013-04-09

申请号：US10777421

申请日：2004-02-12

申请人： Jay T. Young ,  Ian L. McEwen

发明人： Jay T. Young ,  Ian L. McEwen

IPC分类号： G06F21/00

CPC分类号： G01R31/318516 ,  G01R31/31704 ,  G06F17/5054 ,  G06F17/5077

摘要： Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of untested input or output terminals for each untested resource. The number of untested input or output terminals (whichever is larger) for each routing resource determines the minimum number of additional test designs in which the routing resource must be included. The resulting prioritization can be utilized by a router, for example, to first include in test designs those routing resources that must be included in the largest remaining number of test designs. The described prioritization methods can also be used to select one of two or more test designs that should be included in the overall test suite. In each case, the overall number of test designs is reduced.

摘要翻译： 在可编程逻辑器件（PLD）中对未经测试的路由资源进行优先级排序以生成包含最少数量的测试设计的测试套件的方法。 未经测试的路由资源基于每个未测试资源的未测试的输入或输出终端的数量被优先排列（例如，放置在有序列表中）。 每个路由资源的未测试的输入或输出终端数量（以较大者为准）决定必须包含路由资源的其他测试设计的最小数量。 所产生的优先级可由路由器利用，例如，首先在测试设计中包括必须包含在最大剩余数量的测试设计中的路由资源。 所描述的优先级方法也可用于选择应包括在整个测试套件中的两个或多个测试设计之一。 在每种情况下，测试设计的总数减少。

公开(公告)号：US07890917B1

公开(公告)日：2011-02-15

申请号：US12008848

申请日：2008-01-14

申请人： Jay T. Young ,  Jeffrey M. Mason

发明人： Jay T. Young ,  Jeffrey M. Mason

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： Method and apparatus for providing secure intellectual property (IP) cores for a programmable logic device (PLD) are described. An aspect of the invention relates to a method of securely distributing an IP core for PLDs. A circuit design is generated for the IP core, the circuit design being re-locatable in a programmable fabric for PLDs. The circuit design is encoded to produce at least one partial configuration bitstream. Implementation data is generated for utilizing the IP core as a reconfigurable module in top-level circuit designs. The at least one partial configuration bitstream and the implementation data are delivered to users of the PLDs.

摘要翻译： 描述了用于为可编程逻辑器件（PLD）提供安全知识产权（IP）内核的方法和装置。 本发明的一个方面涉及一种可靠地分配用于PLD的IP核的方法。 为IP核生成电路设计，电路设计可重新定位在PLD的可编程结构中。 电路设计被编码以产生至少一个部分配置比特流。 生成实现数据，以将IP核作为顶级电路设计中的可重新配置模块。 将至少一个部分配置比特流和实现数据传送给PLD的用户。

公开(公告)号：US07249335B1

公开(公告)日：2007-07-24

申请号：US11590132

申请日：2006-10-31

申请人： Jay T. Young ,  Jeffrey V. Lindholm ,  Sridhar Krishnamurthy

发明人： Jay T. Young ,  Jeffrey V. Lindholm ,  Sridhar Krishnamurthy

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.

摘要翻译： 将设计路由到可编程逻辑器件（PLD）中以提高将多帧写入（MFW）压缩技术应用于所得配置比特流的有效性的方法。 这些方法应用放置模式和/或路由模板，以鼓励在路由设计中包含多个重复的路由路径。 复制的路由路径导致重复的配置数据。 因此，在PLD中实现路由设计的配置比特流包括复制的配置数据帧的数量，并且非常适合于受益于MFW压缩技术。

公开(公告)号：US07509617B1

公开(公告)日：2009-03-24

申请号：US11225248

申请日：2005-09-12

申请人： Jay T. Young

发明人： Jay T. Young

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of the FPGA, reducing overall design time and PROM storage space needed for the design. The design rules for the method include a requirement that the same frames oriented in the same relative location be available in dynamic areas where a bit stream will be located. Further, the rules require the same relative communication interfaces be available between the dynamic areas and static areas when the bit stream is relocated. Additionally the design rules require global resources, such as clock resources used by the static areas remain the same when the bit stream is relocated.

摘要翻译： 用于生成FPGA设计的方法通过允许在FPGA的不同区域内重新定位相同的单个比特流来实现部分重新配置，从而减少设计所需的总体设计时间和PROM存储空间。 该方法的设计规则包括要求在相同相对位置定向的相同帧在位流将位于的动态区域中可用。 此外，当重新定位位流时，规则要求在动态区域和静态区域之间具有相同的相对通信接口。 此外，设计规则需要全局资源，例如当位流重新定位时，静态区域使用的时钟资源保持不变。

公开(公告)号：US07058919B1

公开(公告)日：2006-06-06

申请号：US10696357

申请日：2003-10-28

申请人： Jay T. Young ,  Sridhar Krishnamurthy ,  Jeffrey V. Lindholm ,  Ian L. McEwen

发明人： Jay T. Young ,  Sridhar Krishnamurthy ,  Jeffrey V. Lindholm ,  Ian L. McEwen

IPC分类号： G06F17/50

CPC分类号： G01R31/318516 ,  G01R31/31704

摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.

摘要翻译： 直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。 使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。 网络基于源标识，网络的负载被标识为路由器负载目标。 路由器然后用于从目标路由资源转发到网络上的一个负载。 可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。 可以创建其他测试设计来测试剩余的目标路由资源。 在其他实施例中，路由器首先向前路由，然后向后路由。