公开(公告)号：US07505303B2

公开(公告)日：2009-03-17

申请号：US11644447

申请日：2006-12-22

Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan

Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan

IPC: G11C11/00

CPC classification number: G11C16/3418 ,  G11C14/00 ,  G11C14/0063

Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

Abstract translation: 公开了一种用于干扰半导体存储器的非易失性部分中的擦除存储器位置结构的系统和方法。 本发明对半导体存储器的处于编程状态的非易失性部分的第一存储位置和处于擦除状态的半导体存储器的非易失性部分的第二存储器位置施加电压，以便 以使第一存储器位置被编程并且将第二存储器位置从编程状态转变到擦除状态。