中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.011 seconds)

    CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST
    2.
    发明申请
    CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST 有权
    电容器电源遏制器保护和可靠性测试

    公开(公告)号：US20130170312A1

    公开(公告)日：2013-07-04

    申请号：US13340439

    申请日：2011-12-29

    Applicant: Srikanth _ Reddy Tiyyagura ,  David Wright ,  David Still ,  Jayant Ashokkumar

    Inventor： Srikanth _ Reddy Tiyyagura ,  David Wright ,  David Still ,  Jayant Ashokkumar

    IPC: G11C5/14 ,  G01R19/00

    CPC classification number: G01R31/40 ,  G01R31/028

    Abstract: A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”).

    Abstract translation: 用于电容器电源的验证电路在两个时间点测量电容器两端的至少两个电压，两个时间点定义时间间隔dT。 确定时间间隔dT的电压dV的变化。 通过从时间间隔dT和/或电压变化dV导出完成操作的总需要时间或总要求电压，并且比较总需要的时间或总需求来启动由电容器供电的操作 电压分别为预定必需的总时间或预定的必要总电压（“时间间隔测试”）。

    METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY
    3.
    发明申请
    METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY 有权
    在非易失性静态随机访问存储器中实现复位功能的方法和装置

    公开(公告)号：US20120213027A1

    公开(公告)日：2012-08-23

    申请号：US13216546

    申请日：2011-08-24

    Applicant: James D. Allan ,  Jayant Ashokkumar

    Inventor： James D. Allan ,  Jayant Ashokkumar

    IPC: G11C5/14

    CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

    Abstract translation: 公开了一种用于复位半导体存储器的系统和方法。 本发明使用阵列复位电路来独立地驱动易失性存储器单元的高位或低位的位线，以将单个存储器单元或具有全0或全部1的阵列中的所有存储单元复位。

    Capacitor power source tamper protection and reliability test
    4.
    发明授权
    Capacitor power source tamper protection and reliability test 有权
    电容器电源篡改保护和可靠性测试

    公开(公告)号：US08559262B2

    公开(公告)日：2013-10-15

    申请号：US13340439

    申请日：2011-12-29

    Applicant: Srikanth Reddy Tiyyagura ,  David Still ,  Jayant Ashokkumar ,  David G Wright

    Inventor： Srikanth Reddy Tiyyagura ,  David Still ,  Jayant Ashokkumar ,  David G Wright

    IPC: G11C5/14

    CPC classification number: G01R31/40 ,  G01R31/028

    Abstract: A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”).

    Abstract translation: 用于电容器电源的验证电路在两个时间点测量电容器两端的至少两个电压，两个时间点定义时间间隔dT。 确定时间间隔dT的电压dV的变化。 通过从时间间隔dT和/或电压变化dV导出完成操作的总需要时间或总要求电压，并且比较总需要的时间或总需求来启动由电容器供电的操作 电压分别为预定必需的总时间或预定的必要总电压（“时间间隔测试”）。

    Method and apparatus to implement a reset function in a non-volatile static random access memory
    5.
    发明授权
    Method and apparatus to implement a reset function in a non-volatile static random access memory 有权
    在非易失性静态随机存取存储器中实现复位功能的方法和装置

    公开(公告)号：US08315096B2

    公开(公告)日：2012-11-20

    申请号：US13216546

    申请日：2011-08-24

    Applicant: James D Allan ,  Jayant Ashokkumar

    Inventor： James D Allan ,  Jayant Ashokkumar

    IPC: G11C14/00

    CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

    Abstract: The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

    Abstract translation: 通过将电源接地到易失性存储器单元并将第一位线驱动到易失性存储器单元至第一限定状态来设置易失性存储器单元的状态。 第一位线的第一定义状态可以独立于到易失性存储器单元的第二位线的定义状态来控制。 易失性存储器单元的字线被驱动到字线状态，并且向易失性存储单元的电源不接地。

    Method and apparatus to implement a reset function in a non-volatile static random access memory
    9.
    发明申请
    Method and apparatus to implement a reset function in a non-volatile static random access memory 审中-公开
    在非易失性静态随机存取存储器中实现复位功能的方法和装置

    公开(公告)号：US20080151654A1

    公开(公告)日：2008-06-26

    申请号：US11644165

    申请日：2006-12-22

    Applicant: James D. Allan ,  Jayant Ashokkumar

    Inventor： James D. Allan ,  Jayant Ashokkumar

    IPC: G11C7/20 ,  G11C7/12

    CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

    Abstract translation: 公开了一种用于复位半导体存储器的系统和方法。 本发明使用阵列复位电路来独立地驱动易失性存储器单元的高位或低位的位线，以将单个存储器单元或具有全0或全部1的阵列中的所有存储单元复位。

    Method and apparatus to create an erase disturb on a non-volatile static random access memory cell
    10.
    发明申请
    Method and apparatus to create an erase disturb on a non-volatile static random access memory cell 有权
    在非易失性静态随机存取存储器单元上产生擦除干扰的方法和装置

    公开(公告)号：US20080151643A1

    公开(公告)日：2008-06-26

    申请号：US11644447

    申请日：2006-12-22

    Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan

    Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan

    IPC: G11C16/00

    CPC classification number: G11C16/3418 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

    Abstract translation: 公开了一种用于干扰半导体存储器的非易失性部分中的擦除存储器位置结构的系统和方法。 本发明对半导体存储器的处于编程状态的非易失性部分的第一存储位置和处于擦除状态的半导体存储器的非易失性部分的第二存储器位置施加电压，以便 以使第一存储器位置被编程并且将第二存储器位置从编程状态转变到擦除状态。

Patent Agency Ranking