公开(公告)号：US20120213027A1

公开(公告)日：2012-08-23

申请号：US13216546

申请日：2011-08-24

Applicant: James D. Allan ,  Jayant Ashokkumar

Inventor： James D. Allan ,  Jayant Ashokkumar

IPC: G11C5/14

CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

Abstract: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

Abstract translation: 公开了一种用于复位半导体存储器的系统和方法。 本发明使用阵列复位电路来独立地驱动易失性存储器单元的高位或低位的位线，以将单个存储器单元或具有全0或全部1的阵列中的所有存储单元复位。

公开(公告)号：US06324107B1

公开(公告)日：2001-11-27

申请号：US09639454

申请日：2000-08-15

Applicant: James D. Allan ,  John J. Silver ,  Keith A. Ford

Inventor： James D. Allan ,  John J. Silver ,  Keith A. Ford

IPC: G11C700

CPC classification number: G11C29/26

Abstract: An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry. In a further embodiment, a plurality of cells of an asynchronous memory device may be read in parallel and an output signal indicative of a logical combination of logic states of the plurality of cells and a test signal at the speed of the slowest cell access time produced thereby.

Abstract translation: 异步存储器件包括并行测试电路，其被配置为提供该器件的最慢位访问时间的量度。 并行测试电路可以包括被配置为从设备的多个单元接收逻辑信号并且提供指示多个单元的逻辑状态的第一输出信号的第一电路。 并行测试电路还可以包括被配置为接收第一输出信号并产生指示第一输出信号的逻辑状态的第二输出信号的第二电路。 并行测试电路可以是在存储器件的读取路径中使用的相同的电路，并且可以被配置为使得第二输出信号以最慢的位访问时间产生。 所测试的多个单元可以包括设备的冗余单元。 这种冗余对于测试电路是透明的。 在另一实施例中，可以并行地读取异步存储器件的多个单元，并且产生指示多个单元的逻辑状态的逻辑组合的输出信号和以最慢单元访问时间的速度产生的测试信号 从而。

公开(公告)号：US4322824A

公开(公告)日：1982-03-30

申请号：US93776

申请日：1979-11-13

Applicant: James D. Allan

Inventor： James D. Allan

IPC: G11C11/401 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/06 ,  H01L27/11 ,  G11C11/40

CPC classification number: G11C11/412 ,  H01L27/0688 ,  H01L27/1112 ,  Y10S257/904

Abstract: A static Random-Access-Memory having a single bit line between each pair of adjacent columns of memory cells, implemented in a self-aligned, N-channel, silicon-gate system. Resistor element load devices are made in second-level polycrystalline silicon by an ion implant step. The second-level polycrystalline silicon is insulated from the first-level polycrystalline silicon by a multiple oxide insulation layer. An additional word line for each row of memory cells provides differentiation between adjacent memory cells sharing a single bit line.

Abstract translation: 一种静态随机存取存储器，其在每对相邻的存储单元列之间具有在自对准N沟道硅栅极系统中实现的单个位线。 电阻元件负载器件通过离子注入步骤在二级多晶硅中制成。 二级多晶硅通过多重氧化物绝缘层与第一级多晶硅绝缘。 每行存储器单元的附加字线提供了在共享单个位线的相邻存储器单元之间的区别。

公开(公告)号：US20080155186A1

公开(公告)日：2008-06-26

申请号：US11644641

申请日：2006-12-22

Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan

Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan

IPC: G06F12/12

CPC classification number: G11C16/10 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/0433

Abstract: A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Abstract translation: 公开了一种用于编程和擦除半导体存储器的系统和方法。 更具体地，本发明使用半导体存储器的易失性存储器部分的位线来编程和擦除半导体存储器的非易失性部分。

公开(公告)号：US4656612A

公开(公告)日：1987-04-07

申请号：US672907

申请日：1984-11-19

Applicant: James D. Allan

Inventor： James D. Allan

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

CPC classification number: G11C11/4076

Abstract: In a DRAM, current surges during sense and restore operations are compensated. Peak current through sense amplifiers is stabilized through initiation of the sense and restore operations during the chip active period and completion of the sense and restore operation during the chip precharge period. The delay between first and second sensing signals is controlled to be longer for those temperature and power supply conditions under which the chip is operating fastest. Correspondingly, the delay between first and second sensing signals is made shorter for those temperature and power supply conditions under which the chip is operating slowest. Overall peak current is limited to that drawn through small transistors used to begin turning on the sense amplifier. The duration of the second sensing signal is responsive to the temperature and power supply variation so it endures for an acceptable period in which to complete the sense and restore function. The second sensing signal timing is not determined by the first sensing signal.

Abstract translation: 在DRAM中，感测和恢复操作期间的电流波动得到补偿。 通过感测放大器的峰值电流通过在芯片有效周期期间启动感测和恢复操作并且在芯片预充电期间完成感测和恢复操作来稳定。 对于芯片运行最快的温度和电源条件，第一和第二感测信号之间的延迟被控制得更长。 相应地，对于芯片运行最慢的温度和电源条件，第一和第二感测信号之间的延迟变短。 总峰值电流仅限于通过用于开始接通读出放大器的小型晶体管。 第二感测信号的持续时间响应于温度和电源变化，因此它可以忍受完成感测和恢复功能的可接受的时间段。 第二感测信号定时不由第一感测信号确定。

公开(公告)号：US07505303B2

公开(公告)日：2009-03-17

申请号：US11644447

申请日：2006-12-22

Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan

Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan

IPC: G11C11/00

CPC classification number: G11C16/3418 ,  G11C14/00 ,  G11C14/0063

Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

Abstract translation: 公开了一种用于干扰半导体存储器的非易失性部分中的擦除存储器位置结构的系统和方法。 本发明对半导体存储器的处于编程状态的非易失性部分的第一存储位置和处于擦除状态的半导体存储器的非易失性部分的第二存储器位置施加电压，以便 以使第一存储器位置被编程并且将第二存储器位置从编程状态转变到擦除状态。

公开(公告)号：US6005814A

公开(公告)日：1999-12-21

申请号：US54654

申请日：1998-04-03

Applicant: Sean B. Mulholland ,  James D. Allan

Inventor： Sean B. Mulholland ,  James D. Allan

IPC: G01R31/317 ,  G11C7/10 ,  G11C29/46 ,  G11C7/00

CPC classification number: G11C29/46 ,  G01R31/31701 ,  G11C7/1045

Abstract: A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise "illegal" operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.

Abstract translation: 用于在集成电路（例如存储器件）中输入测试模式的鲁棒系统极大地消除了无意进入测试模式的可能性，而且通过精确的地址和控制引脚序列来提供访问系统。 通过使用存在于集成电路上的现有控制引脚作为一系列锁存器的时钟信号输入，本方案设置了具有预定值的地址数，以便仅当所有地址处于 正确的值。 该键与时钟信号输入相结合，允许测试模式使能信号以一系列方式通过每个锁存器。 通过进一步要求在集成电路的另一“非法”操作期间输入键的地址序列，本方案进一步确保避免无意进入测试模式。

公开(公告)号：US4698526A

公开(公告)日：1987-10-06

申请号：US788442

申请日：1985-10-17

Applicant: James D. Allan

Inventor： James D. Allan

IPC: H01L21/8238 ,  H01L27/092 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/094 ,  H03K17/10 ,  H03K17/687 ,  H03K19/092

CPC classification number: H03K19/0948 ,  H03K19/01721 ,  H03K19/018521

Abstract: An input buffer has input and output inverters. An n-channel transistor is coupled as a source follower between the inverters. The buffer receives a TTL input and provides a CMOS output. The source follower transistor has a large channel width and provides substantial pullup. The output inverter stage can be made larger. A p-channel transistor in parallel with the n-channel source follower transistor permits the internal node to reach a full Vcc level. Another n-channel transistor driven by the input signal permits the node to reach ground.

Abstract translation: 输入缓冲器具有输入和输出反相器。 n沟道晶体管作为逆变器之间的源极跟随器耦合。 缓冲器接收TTL输入并提供CMOS输出。 源极跟随器晶体管具有大的沟道宽度并且提供实质的上拉。 输出变频器级可以做大。 与n沟道源极跟随器晶体管并联的p沟道晶体管允许内部节点达到完整的Vcc电平。 由输入信号驱动的另一个n沟道晶体管允许节点到达地。

公开(公告)号：US08315096B2

公开(公告)日：2012-11-20

申请号：US13216546

申请日：2011-08-24

Applicant: James D Allan ,  Jayant Ashokkumar

Inventor： James D Allan ,  Jayant Ashokkumar

IPC: G11C14/00

CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

Abstract: The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

Abstract translation: 通过将电源接地到易失性存储器单元并将第一位线驱动到易失性存储器单元至第一限定状态来设置易失性存储器单元的状态。 第一位线的第一定义状态可以独立于到易失性存储器单元的第二位线的定义状态来控制。 易失性存储器单元的字线被驱动到字线状态，并且向易失性存储单元的电源不接地。

公开(公告)号：US07518916B2

公开(公告)日：2009-04-14

申请号：US11644819

申请日：2006-12-22

Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan ,  John Roger Gill

Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan ,  John Roger Gill

IPC: G11C16/04

CPC classification number: G11C14/00 ,  G11C14/0063

Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Abstract translation: 公开了一种用于对半导体存储器中的非易失性部分的两侧进行编程的系统和方法。 本发明擦除然后对nvSRAM的非易失性部分中的存储器堆栈进行编程。