公开(公告)号：US07916510B1

公开(公告)日：2011-03-29

申请号：US12844321

申请日：2010-07-27

Applicant: Alexei Starovoitov ,  Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Alexei Starovoitov ,  Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G06F17/30985

Abstract: An apparatus and method of programming a search engine to implement regular expression search operations are disclosed that selectively transform a source regular expression into an equivalent reformulated regular expression in response to a determination of the architectural characteristics of the search engine. In this manner, the regular expression can be reformulated to optimize the configuration and available resources of the associated search engine.

Abstract translation: 公开了一种对搜索引擎进行编程以实现正则表达式搜索操作的装置和方法，其响应于确定搜索引擎的架构特征而选择性地将源正则表达式变换为等效的重新排列的正则表达式。 以这种方式，可以重新规定正则表达式以优化相关搜索引擎的配置和可用资源。

公开(公告)号：US07924590B1

公开(公告)日：2011-04-12

申请号：US12844235

申请日：2010-07-27

Applicant: Alexei Starovoitov ,  Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Alexei Starovoitov ,  Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C15/00

CPC classification number: G06F8/427 ,  G11C15/00

Abstract: A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.

Abstract translation: 内容搜索系统包括CAM设备，编译器和图像加载器。 包括多行CAM单元的CAM设备和通过可编程互连结构（PRS）选择性互连的多个计数器电路执行正则表达式搜索操作。 编译器选择性地将正则表达式转换成多个不同的位组，并且图像加载器将对应的位组加载到CAM单元中，并将其加载到多个控制PRS的配置的存储器元件中并进入计数器电路。

公开(公告)号：US07881125B2

公开(公告)日：2011-02-01

申请号：US12873122

申请日：2010-08-31

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。

公开(公告)号：US07660140B1

公开(公告)日：2010-02-09

申请号：US12341754

申请日：2008-12-22

Applicant: Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

公开(公告)号：US07656716B1

公开(公告)日：2010-02-02

申请号：US12341284

申请日：2008-12-22

Applicant: Varadarajan Srinivasan ,  Maheshwaran Srinivasan ,  Sachin Joshi ,  Sandeep Khanna ,  De Cai Li

Inventor： Varadarajan Srinivasan ,  Maheshwaran Srinivasan ,  Sachin Joshi ,  Sandeep Khanna ,  De Cai Li

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A system for searching an input string for a number of regular expressions includes a search block and a compiler. The search block includes a plurality of content addressable memory (CAM) devices, wherein each of the CAM devices is differently configured to implement search operations for regular expressions having a unique level of complexity. The compiler is configured to determine the complexity level of each of the regular expressions, and is configured to store each regular expression in a selected one of the CAM devices according to its complexity level.

Abstract translation: 用于搜索用于多个正则表达式的输入字符串的系统包括搜索块和编译器。 搜索块包括多个内容可寻址存储器（CAM）设备，其中每个CAM设备被不同地配置为对具有独特复杂度的正则表达式实现搜索操作。 编译器被配置为确定每个正则表达式的复杂度级别，并且被配置为根据其复杂度级别将所选择的一个CAM设备中的每个正则表达式存储。

公开(公告)号：US20130009619A1

公开(公告)日：2013-01-10

申请号：US13618652

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: G05F1/10

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US08274265B1

公开(公告)日：2012-09-25

申请号：US12028774

申请日：2008-02-08

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: G05F1/59 ,  G05F1/618

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US07876590B2

公开(公告)日：2011-01-25

申请号：US12873183

申请日：2010-08-31

Applicant: Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract translation: 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

公开(公告)号：US07826242B2

公开(公告)日：2010-11-02

申请号：US12619607

申请日：2009-11-16

Applicant: Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract translation: 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

公开(公告)号：US07821844B2

公开(公告)日：2010-10-26

申请号：US12617369

申请日：2009-11-12

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。