Abstract:
A panel for a flat panel display device is disclosed, which includes a substrate having signal wires and terminals respectively connected to the signal wires, each terminal having first, second and third conducting layer, an insulating layer, a protection layer, contact holes connected between the first conducting layer and the third conducting layer, and contact holes connected between the second conducting layer and the third conducting layer, the insulating layer being sandwiched in between the second conducting layer and the substrate, the first conducting layer being sandwiched in between the protection layer and the insulating layer, the protection layer being sandwiched in between the first conducting layer and the third conducting layer or the second conducting layer and the third conducting layer, the first conducting layer being isolated from the second conducting layer.
Abstract:
A TFT liquid crystal display device is disclosed, which includes two substrates and a liquid crystal layer provided in between the substrates, one substrate having a surface providing with a plurality of data signal lines, a plurality of scan lines, a plurality of pixel electrodes, and a plurality of functional components having source electrode, gate electrodes and drain electrodes. Moreover, the projection of one of the signal electrode and the drain electrode on the gate electrode having at least one bridging zone and one conducting zone. The width of the bridging zone in the direction in parallel to one side of the gate electrode is smaller than the width of the conducting zone in the direction in parallel to the side of the gate electrode.
Abstract:
A pixel structure is provided. The pixel structure includes a scan line, a gate, a first dielectric layer, a channel layer, a source, a drain, a data line, a second dielectric layer, and a pixel electrode. The gate is electrically connected to the scan line and has a first notch. The first dielectric layer covers the scan line and the gate. The channel layer is disposed on the first dielectric layer over the gate and exposed by the first notch. The source and the drain are disposed on the channel layer. Part of the drain is located over the first notch. The data line is disposed on the first dielectric layer and electrically connected to the source. The second dielectric layer covers the source, the drain and the data line. The pixel electrode is disposed on the second dielectric layer and electrically connected to the drain.
Abstract:
A transistor that at least has one of the following characteristics: First, the gate electrode is located outside the gate line, such that the whole transistor is located outside the gate line. Second, the projection of the semiconductor layer on the substrate is totally located inside the projection of the gate electrode on the substrate. Third, the drain cross the gate electrode, such that the projection of the cross-section is totally located inside the projection of the gate electrode. Final, the separated distance between the gate line, the gate electrode, the drain and the source is adjusted to let the variation of each of Cgd and Cds be not obviously affected by the alignment deviation.