公开(公告)号：US6052323A

公开(公告)日：2000-04-18

申请号：US354839

申请日：1999-07-16

Applicant: J. Patrick Kawamura

Inventor： J. Patrick Kawamura

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/06

Abstract: A memory circuit (10) provides reduced array sense amplifier circuitry (20, 22) for a memory cell array (24, 26, 28, 30), which has a plurality of memory cells (340) for electrically storing data. A plurality of bitlines (260) are associated with a memory cell array (26) for carrying data to and from the memory cells therein. At least one sense amplifier circuit (16) includes circuitry (332, 334) for addressing selected memory cells via column select lines, and for communicating with an external source of address signals. A local sense amplifier circuit (20, 22) includes circuitry (262, 266) for communicating with the sense amplifier circuit through the selected bitlines. The local sense amplifier circuit also includes circuitry (234, 238) for communicating with other bitlines (232, 236) for addressing other memory cells (28), and further for transmitting data to and from the other memory cells along the selected bitlines, in cooperation with the sense amplifier (16).

Abstract translation: 存储器电路（10）为具有用于电存储数据的多个存储单元（340）的存储单元阵列（24,26,28,30）提供缩小的阵列读出放大器电路（20,22）。 多个位线（260）与用于将数据传送到其中的存储器单元的存储单元阵列（26）相关联。 至少一个读出放大器电路（16）包括用于经由列选择线寻址所选择的存储器单元并用于与外部地址信号源进行通信的电路（332,334）。 本地读出放大器电路（20,22）包括用于通过选定位线与读出放大器电路进行通信的电路（262,266）。 本地读出放大器电路还包括用于与其他位线（232,236）进行通信以用于寻址其他存储器单元（28）的电路（234,238），并且还用于沿着所选择的位线向和从其它存储器单元发送数据， 与感测放大器（16）的配合。

公开(公告)号：US5939923A

公开(公告)日：1999-08-17

申请号：US971809

申请日：1997-11-17

Applicant: J. Patrick Kawamura

Inventor： J. Patrick Kawamura

IPC: H03K19/00 ,  H03K19/0185 ,  H03K5/00

CPC classification number: H03K19/0016 ,  H03K19/018585

Abstract: A selectable low power signal line (10) is provided that includes a driver circuit (12) connected to receive an input signal for transmission and to receive a mode select signal (SELECT). The driver circuit (12) has a low power mode and a full power mode selectable responsive to the mode select signal (SELECT). The driver circuit (12) is operable, when in the full power mode, to drive an output signal at a full swing of the input signal. When in the low power mode, the driver circuit (12) is operable to drive the output signal at a fraction of the full swing of the input signal. A physical signal line (14) is connected to receive the output signal of the driver circuit (12) and to carry the output signal. A receiver circuit (16) is connected to receive the signal on the physical signal line (14) and is also connected to receive the mode select signal (SELECT). The receiver circuit (16) has a low power and full power mode selectable responsive to the mode select signal (SELECT). The receiver circuit (16) is operable, when in the full power mode, to drive an output signal at a full swing of the signal on the physical signal line (14). When in the low power mode, the receiver circuit (16) is operable to convert the signal on the physical signal line (14) from a fraction of the full swing of the input signal to a full swing of the input signal and to drive the output signal at the full swing.

Abstract translation: 提供了一种可选择的低功率信号线（10），其包括被连接以接收用于传输的输入信号并且接收模式选择信号（SELECT）的驱动器电路（12）。 驱动电路（12）具有低功率模式和响应于模式选择信号（SELECT）可选择的全功率模式。 当处于全功率模式时，驱动器电路（12）可以在输入信号的完全摆动时驱动输出信号。 当处于低功率模式时，驱动电路（12）可操作以以输入信号的全部摆幅的一小部分驱动输出信号。 物理信号线（14）被连接以接收驱动电路（12）的输出信号并携带输出信号。 接收器电路（16）被连接以接收物理信号线（14）上的信号，并且还被连接以接收模式选择信号（SELECT）。 接收器电路（16）具有响应于模式选择信号（SELECT）可选择的低功率和全功率模式。 当处于全功率模式时，接收器电路（16）可以在物理信号线（14）上的信号的完全摆动时驱动输出信号。 当处于低功率模式时，接收器电路（16）可操作以将物理信号线（14）上的信号从输入信号的全摆幅的一小部分转换为输入信号的全摆幅，并驱动 全速输出信号。

公开(公告)号：US6115321A

公开(公告)日：2000-09-05

申请号：US110620

申请日：1998-07-06

Applicant: Jeffrey E. Koelling ,  J. Patrick Kawamura

Inventor： Jeffrey E. Koelling ,  J. Patrick Kawamura

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/1078

Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (220) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.

Abstract translation: 用于与系统时钟信号同步操作的存储器电路被设计为具有以行和列排列的多个存储器单元的存储器阵列（250,252,254,256）。 响应于第一列地址信号，多列列解码电路（502）的每列解码电路在相应的列选择线（108）产生选择信号。 多个读出放大器电路（202）分组布置。 每个读出放大器电路耦合到相应的存储单元列。 每个读出放大器电路包括用于将读出放大器耦合到相应的数据线（203）的选择晶体管。 一组读出放大器电路的每个选择晶体管的控制端子连接到相应的列选择线。 数据序列电路（218）被耦合以响应于系统时钟信号的第一周期从四个相应的数据线（210,212,214,216）接收四个数据位。 数据序列电路响应于控制信号和第二列地址信号产生四个有序的数据位。 寄存器电路（220）被耦合以接收四个有序的数据位。 寄存器电路在系统时钟信号的第一周期之后响应于系统时钟信号的多个周期而产生四个有序数据位的序列。