公开(公告)号：US6137331A

公开(公告)日：2000-10-24

申请号：US184533

申请日：1998-11-02

申请人： Rafael Peset Llopis

发明人： Rafael Peset Llopis

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/12 ,  H03K3/286 ,  H03K3/356

CPC分类号： H03K3/012 ,  H03K3/037

摘要： The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.

摘要翻译： 电子电路包含双边沿触发触发器，它在时钟信号的上升沿和下降沿都加载数据。 时钟信号由具有用于接收源信号的使能输入和源极输入的时钟供应电路提供。 在使能输入的使能信号切换到有效状态之后，与所述最早可用边沿的极性无关地，时钟供应电路切换来自源信号的最早可用边沿的时钟信号。