Abstract:
A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration executes by consuming completed operand sets from a designated input tag space (e.g., in a content addressable memory) until the operand sets are exhausted. At that point, the configuration is replaced by another configuration. The execution of a configuration may be triggered by system events, including by the completion of one or more other configurations. Each configuration has a list of inputs on which it depends to form complete operand sets. As other configurations that provide an input complete, a dependency flag is set in each dependent configuration. As each flag is set, the complete set of flags is checked for that configuration; if all the input flags for any configuration are set, then that configuration is scheduled for execution.
Abstract:
A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.
Abstract:
Higher performance is gained through a new architecture which implements a new method of computational resource allocation, utilization and programming based on the concept of Worm-hole Run-Time Reconfiguration (RTR). A stream-driven Worm-hole RTR methodology extends contemporary data-flow paradigms to utilize the dynamic creation of operators and pathways, based upon stream processing in which parcels of data move through custom created pathways and interact with other parcels to achieve the desired computation. These parcels independently allocate the necessary computing resources and data paths as they navigate through the platform. The Worm-hole RTR platform consists of a large number of configurable functional units that perform the custom computations and rich, configurable interconnection pathways between the functional units. Once a computational pathway has been established (sensitized) by the head of the stream parcel, data are processed through the pathway with zero overhead. All ports entering the computing platform serve both to configure operations and pathways and to pass computational data streams. As a result, programming and configuration is not limited to a single port. Configuration through multiple independent ports allows greater concurrency, faster reconfiguration, and fewer computational dependencies, all with relatively low cost in silicon.
Abstract:
A side channel communications system disclosed herein includes a receiver device with an internal circuitry where the operational speed of the internal circuitry changes in response to an external signal. When the receiver device receives an external signal, the operational speed of the internal circuitry changes. A detector detects the change in the operational speed of the internal circuitry to generate an output value, which is decoded to determine the information communicated by the external signal. In one implementation of the side channel communications system, the external transmitter communicates the external signal in the form of a temperature signal. Alternatively, the external transmitter communicates the external signal in the form of a change in the supply voltage.
Abstract:
An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.
Abstract:
A display apparatus described herein includes a display screen and a display processor. The display processor includes a plurality of function units that comprise functions that are representative of data that is desirably displayed on the display screen. The display processor is configured to receive configurations, compositions, and/or parameters for the plurality of function units. In addition, the display processor displays data on the display screen based at least in part upon output of the plurality of function units.
Abstract:
An input device includes an array of adjacent capacitive sensors arranged into rows and columns. Each capacitive sensor exhibits a capacitance characteristic when in proximity to a conductive element. A plurality of mechanical hysteresis mechanisms are each deposited on and in contact with each of the capacitive sensors and configured to be actuated by a corresponding push button. Each capacitive sensor exhibits an electrical characteristic upon actuation of the corresponding mechanical hysteresis mechanism. An insulating overlay layer positioned over the array of capacitive sensors and the plurality of mechanical hysteresis mechanisms defines each push button and defines a surface for accommodating the conductive element.
Abstract:
A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.