公开(公告)号：US12124392B2

公开(公告)日：2024-10-22

申请号：US18230375

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Steven C. Woo

IPC: G06F13/40 ,  G06N3/045 ,  H01L25/065

CPC classification number: G06F13/4027 ,  G06N3/045 ,  H01L25/0652

Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.

公开(公告)号：US12093161B2

公开(公告)日：2024-09-17

申请号：US17326114

申请日：2021-05-20

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Ori Isachar ,  Tal Lazmi

IPC: G06F11/30 ,  G01R31/317 ,  G06F11/34 ,  G06F13/40

CPC classification number: G06F11/348 ,  G01R31/31705 ,  G06F11/3003 ,  G06F11/3065 ,  G06F11/3485 ,  G06F11/349 ,  G06F11/3495 ,  G06F13/4022 ,  G06F13/4027

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.

公开(公告)号：US12086080B2

公开(公告)日：2024-09-10

申请号：US17033728

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： George Chrysos ,  Bhargavi Narayanasetty ,  Jesus Corbal ,  Ching-Kai Liang ,  Chinmay Ashok ,  Francis Tseng

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/4027

Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described. In one embodiment, a hardware accelerator includes a plurality of dataflow execution circuits that each comprise a register file, a plurality of execution circuits, and a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file; a cross dependence network coupled between the plurality of dataflow execution circuits to send data between the plurality of dataflow execution circuits according to a second dataflow operation entry; and a memory execution interface coupled between the plurality of dataflow execution circuits and a cache bank to send data between the plurality of dataflow execution circuits and the cache bank according to a third dataflow operation entry.

公开(公告)号：US12079711B2

公开(公告)日：2024-09-03

申请号：US17186598

申请日：2021-02-26

Applicant: Google LLC

Inventor： Uday Kumar Dasari ,  Olivier Temam ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/063 ,  G06F7/50 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G06F17/16 ,  G06N3/04 ,  G06N3/0464 ,  G06N20/00 ,  G11C11/22 ,  G11C11/54 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06N3/063 ,  G06F15/7896 ,  G06N3/04 ,  G06F7/50 ,  G06F13/1668 ,  G06F13/4027 ,  G06F17/16 ,  G06N3/0464 ,  G06N20/00 ,  G11C11/22 ,  G11C11/54 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

公开(公告)号：US12079471B2

公开(公告)日：2024-09-03

申请号：US17875457

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu

IPC: G06F12/084 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F3/0604 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

公开(公告)号：US12079153B2

公开(公告)日：2024-09-03

申请号：US18199042

申请日：2023-05-18

Applicant: Intel Corporation

Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445

CPC classification number: G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US12074092B2

公开(公告)日：2024-08-27

申请号：US17172756

申请日：2021-02-10

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz

IPC: H01L23/48 ,  G06F13/40 ,  H01L23/528

CPC classification number: H01L23/481 ,  G06F13/4027 ,  H01L23/528

Abstract: Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.

公开(公告)号：US20240259231A1

公开(公告)日：2024-08-01

申请号：US18613640

申请日：2024-03-22

Applicant: Maxim Integrated Products, Inc.

Inventor： Wuguang LIU ,  Stewart MERKEL

IPC: H04L12/40 ,  G06F1/26 ,  G06F13/40 ,  H02J7/00 ,  H04B3/54

CPC classification number: H04L12/40045 ,  G06F1/266 ,  G06F13/4027 ,  G06F13/4059 ,  H02J7/007 ,  H04B3/548 ,  H04L12/40032 ,  H02J2310/22

Abstract: Described herein are embodiments for dual-port communication and power delivery for one-wire applications. Embodiments of one-wire bridge devices are disclosed to provide a dual-port link for two one-wire masters to communicate with one another in a multi-voltage system while intermittently allowing charging voltage. The configuration may be used to set a bidirectional pass through mode that allows level shifted fast logic signals to pass through the two one-wire links. A timer may also be configurable to time-out the pass through mode from edge in-activity. Power may be derived for operation directly from one of the links, eliminating the need for an external power supply when local power is not available. When local power is available, the other one-wire link provides local access and the pass through mode. Such configurations make it easy for a two-contact solution to be both a communication channel and a power supply for battery charging.

公开(公告)号：US12038860B2

公开(公告)日：2024-07-16

申请号：US18149484

申请日：2023-01-03

Applicant: Parallel Wireless, Inc.

Inventor： Ofir Ben Ari Katzav ,  David Johnston ,  Steven Paul Papa

IPC: G06F13/40 ,  G06F13/42 ,  H04B1/16

CPC classification number: G06F13/4027 ,  G06F13/4221 ,  G06F13/4282 ,  H04B1/16 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: Systems, methods and computer software are disclosed for fronthaul. In one embodiment a method is disclosed, comprising: providing a virtual Radio Access Network (vRAN) having a centralized unit (CU) and a distributed unit (DU); and interconnecting the CU and DU over an Input/Output (I/O) bus using Peripheral Component Interconnect-Express (PCIe); wherein the CU and the DU include a PCI to optical converter and an optical to PCI converter.

公开(公告)号：US12026112B2

公开(公告)日：2024-07-02

申请号：US17943183

申请日：2022-09-12

Applicant: AyDeeKay LLC

Inventor： Scott David Kee

IPC: G06F13/36 ,  G06F3/06 ,  G06F12/06 ,  G06F12/0866 ,  G06F13/14 ,  G06F13/16 ,  G06F13/26 ,  G06F13/28 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F21/76

CPC classification number: G06F13/26 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0638 ,  G06F12/0866 ,  G06F13/14 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/76 ,  G06F2213/0062 ,  G06F2213/40 ,  G06F2221/2103

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.