公开(公告)号：US20080143390A1

公开(公告)日：2008-06-19

申请号：US11861924

申请日：2007-09-26

Applicant: Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/413

Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage. The amplifier further includes a pull down circuit and a delay circuit. The delay circuit produces delay between two control signals. The circuit includes a first NOT gate and a second NOT gate operatively coupled to a first latch output node and a second latch output node respectively to provide an output data corresponding to a data stored in a memory cell.

Abstract translation: 读出放大器电路提供具有低电容和低分辨率时间的高速读取操作的高速感测。 读出放大器电路包括具有彼此交叉耦合的第一反相器电路和第二反相器电路的锁存电路。 放大器电路包括分别可操作地耦合到第一反相器电路和第二反相器电路的第一放电装置和第二放电装置。 放大器电路还包括可操作地耦合在第一放电器件和位线之间的第一PMOS晶体管和可操作地耦合在第二放电器件和互补位线之间的第二PMOS晶体管。 放大器电路还包括可操作地耦合在第一放电装置和接地电压之间的第一NMOS晶体管，可操作地耦合在第二放电装置和接地电压之间的第二NMOS晶体管。 放大器还包括下拉电路和延迟电路。 延迟电路在两个控制信号之间产生延迟。 电路包括分别操作地耦合到第一锁存器输出节点和第二锁存器输出节点的第一NOT门和第二NOT门，以提供对应于存储在存储器单元中的数据的输出数据。

公开(公告)号：US20070201287A1

公开(公告)日：2007-08-30

申请号：US11617286

申请日：2006-12-28

Applicant: Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: G11C7/00

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized. the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.

Abstract translation: 公开了一种用于引入自定时存储器中的延迟的新方法。 在所提出的方法中，通过在要延迟的信号的路径上引入电容来引入延迟。 电容通过在电路中使用空闲的躺着金属层来实现。 要延迟的信号通过可编程开关连接到这些空闲的电平。 引入的延迟量取决于信号路径中引入的电容，又依赖于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于在所提出的方法中，利用空闲的金属电容。 该电路可以使用最小量的附加硬件来实现。 由所提出的电路提供的延迟也是存储器单元香料特性和核心寄生电容的函数。