公开(公告)号：US20160019250A1

公开(公告)日：2016-01-21

申请号：US14477972

申请日：2014-09-05

Applicant: Shishir Kumar ,  Jayakumar Panicker

Inventor： Shishir Kumar ,  Jayakumar Panicker

IPC: G06F17/30

CPC classification number: G06F17/30342 ,  G06F17/30598

Abstract: According to an exemplary embodiment, a method for generating an enterprise user group is provided. The method may include receiving a set of attributes for an enterprise network user; receiving one or more enterprise group member identification rules including a similarity distance threshold and a set of target attributes; calculating, using a hardware processor, a similarity assessment score based on the set of target attributes and the set of attributes; and determining, using the hardware processor, whether the enterprise network user is an enterprise group member based on the similarity assessment score and the similarity distance threshold.

Abstract translation: 根据示例性实施例，提供了一种用于生成企业用户组的方法。 该方法可以包括接收企业网络用户的一组属性; 接收包括相似距离阈值和一组目标属性的一个或多个企业组成员识别规则; 基于所述目标属性和所述属性集来计算使用硬件处理器的相似性评估分数; 以及基于所述相似度评估分数和所述相似距离阈值来确定所述硬件处理器是否所述企业网络用户是企业组成员。

公开(公告)号：US20130170275A1

公开(公告)日：2013-07-04

申请号：US13591663

申请日：2012-08-22

Applicant: Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

Inventor： Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

IPC: G11C5/06

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract translation: 双端口SRAM有两个数据存储节点，一个真实的数据和补充数据。 第一下拉晶体管具有形成第一晶体管的漏极区域和与存储器单元的所有其它晶体管有源区域物理隔离的真实数据存储节点的有源。 第二下拉晶体管具有形成第二晶体管的漏极区域的有源区域，该第二晶体管是与存储器单元的所有其它晶体管有源区域物理隔离的互补数据节点。

公开(公告)号：US09910880B2

公开(公告)日：2018-03-06

申请号：US14477972

申请日：2014-09-05

Applicant: Shishir Kumar ,  Jayakumar Panicker

Inventor： Shishir Kumar ,  Jayakumar Panicker

IPC: G06F17/30

CPC classification number: G06F17/30342 ,  G06F17/30598

Abstract: According to an exemplary embodiment, a method for generating an enterprise user group is provided. The method may include receiving a set of attributes for an enterprise network user; receiving one or more enterprise group member identification rules including a similarity distance threshold and a set of target attributes; calculating, using a hardware processor, a similarity assessment score based on the set of target attributes and the set of attributes; and determining, using the hardware processor, whether the enterprise network user is an enterprise group member based on the similarity assessment score and the similarity distance threshold.

公开(公告)号：US07545180B2

公开(公告)日：2009-06-09

申请号：US11861924

申请日：2007-09-26

Applicant: Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

IPC: G01R19/00

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/413

Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage. The amplifier further includes a pull down circuit and a delay circuit. The delay circuit produces delay between two control signals. The circuit includes a first NOT gate and a second NOT gate operatively coupled to a first latch output node and a second latch output node respectively to provide an output data corresponding to a data stored in a memory cell.

Abstract translation: 读出放大器电路提供具有低电容和低分辨率时间的高速读取操作的高速感测。 读出放大器电路包括具有彼此交叉耦合的第一反相器电路和第二反相器电路的锁存电路。 放大器电路包括分别可操作地耦合到第一反相器电路和第二反相器电路的第一放电装置和第二放电装置。 放大器电路还包括可操作地耦合在第一放电器件和位线之间的第一PMOS晶体管和可操作地耦合在第二放电器件和互补位线之间的第二PMOS晶体管。 放大器电路还包括可操作地耦合在第一放电装置和接地电压之间的第一NMOS晶体管，可操作地耦合在第二放电装置和接地电压之间的第二NMOS晶体管。 放大器还包括下拉电路和延迟电路。 延迟电路在两个控制信号之间产生延迟。 电路包括分别操作地耦合到第一锁存器输出节点和第二锁存器输出节点的第一NOT门和第二NOT门，以提供对应于存储在存储器单元中的数据的输出数据。

公开(公告)号：US09584579B2

公开(公告)日：2017-02-28

申请号：US13308757

申请日：2011-12-01

Applicant: Shishir Kumar Agrawal ,  John Alexander Komoroske

Inventor： Shishir Kumar Agrawal ,  John Alexander Komoroske

IPC: H04L29/08 ,  G06F17/30

CPC classification number: H04L67/02 ,  G06F17/30893 ,  H04L67/36

Abstract: A method and system for providing page visibility information are provided herein. Aspects of this disclosure provide an interface by which a browser may make the visibility state of a particular page available to the page itself. The browser may track the visibility state of the page as it changes and store the state in a variable associated with the page. Code executing within the page may query this variable to determine the visibility state and take appropriate action. The browser may provide an application programming interface (API) to allow the page to request the visibility state.

Abstract translation: 本文提供了一种用于提供页面可见性信息的方法和系统。 本公开的方面提供了一种接口，通过该接口，浏览器可以使特定页面的可见性状态可用于页面本身。 浏览器可以跟踪页面的可见性状态，因为它改变并将状态存储在与页面相关联的变量中。 在页面中执行的代码可能会查询此变量以确定可见性状态并采取适当的措施。 浏览器可以提供应用程序编程接口（API）以允许页面请求可见性状态。

公开(公告)号：US20120170393A1

公开(公告)日：2012-07-05

申请号：US13412306

申请日：2012-03-05

Applicant: Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: G11C7/08

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。

公开(公告)号：US08138455B2

公开(公告)日：2012-03-20

申请号：US11617286

申请日：2006-12-28

Applicant: Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: H05B1/02

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized, the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.

Abstract translation: 公开了一种用于引入自定时存储器中的延迟的新方法。 在所提出的方法中，通过在要延迟的信号的路径上引入电容来引入延迟。 电容通过在电路中使用空闲的躺着金属层来实现。 要延迟的信号通过可编程开关连接到这些空闲的电平。 引入的延迟量取决于信号路径中引入的电容，又依赖于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于在所提出的方法中，利用空闲的金属电容，所以可以使用最小量的附加硬件来实现电路。 由所提出的电路提供的延迟也是存储器单元香料特性和核心寄生电容的函数。

公开(公告)号：US20150195156A1

公开(公告)日：2015-07-09

申请号：US13308757

申请日：2011-12-01

Applicant: Shishir Kumar Agrawal ,  John Alexander Komoroske

Inventor： Shishir Kumar Agrawal ,  John Alexander Komoroske

IPC: H04L12/26

CPC classification number: H04L67/02 ,  G06F17/30893 ,  H04L67/36

Abstract: A method and system for providing page visibility information are provided herein. Aspects of this disclosure provide an interface by which a browser may make the visibility state of a particular page available to the page itself. The browser may track the visibility state of the page as it changes and store the state in a variable associated with the page. Code executing within the page may query this variable to determine the visibility state and take appropriate action. The browser may provide an application programming interface (API) to allow the page to request the visibility state.

Abstract translation: 本文提供了一种用于提供页面可见性信息的方法和系统。 本公开的方面提供了一种接口，通过该接口，浏览器可以使特定页面的可见性状态可用于页面本身。 浏览器可以跟踪页面的可见性状态，因为它改变并将状态存储在与页面相关联的变量中。 在页面中执行的代码可能会查询此变量以确定可见性状态并采取适当的措施。 浏览器可以提供应用程序编程接口（API）以允许页面请求可见性状态。

公开(公告)号：US09006841B2

公开(公告)日：2015-04-14

申请号：US13591663

申请日：2012-08-22

Applicant: Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

Inventor： Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract translation: 双端口SRAM有两个数据存储节点，一个真实的数据和补充数据。 第一下拉晶体管具有形成第一晶体管的漏极区域和与存储器单元的所有其它晶体管有源区域物理隔离的真实数据存储节点的有源区域。 第二下拉晶体管具有形成第二晶体管的漏极区域的有源区域，该第二晶体管是与存储器单元的所有其它晶体管有源区域物理隔离的互补数据节点。

公开(公告)号：US08963053B2

公开(公告)日：2015-02-24

申请号：US13412306

申请日：2012-03-05

Applicant: Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: H05B1/02 ,  G11C29/50 ,  G11C7/06 ,  G11C29/14 ,  G11C7/08 ,  G11C7/22 ,  G11C29/12

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。