公开(公告)号：US07426235B1

公开(公告)日：2008-09-16

申请号：US10965938

申请日：2004-10-15

申请人： Stephen D. Anderson ,  David E. Tetzlaff ,  Michael J. Gaboury ,  Matthew L. Bibee

发明人： Stephen D. Anderson ,  David E. Tetzlaff ,  Michael J. Gaboury ,  Matthew L. Bibee

IPC分类号： H04B1/38

CPC分类号： H04L25/03885 ,  H04L25/03343 ,  H04L2025/03802

摘要： Circuitry for equalizing a high data rate serial data stream that receives low frequency and high frequency test tones, accurately measures an amount of attenuation experienced by the high frequency test tone in relation to the low frequency test tone, and accordingly, produces equalization data that results in a corresponding amount of equalization or pre-emphasis being added to an outgoing signal. More specifically, however, the present invention includes both open loop and closed loop systems for equalizing or adding pre-emphasis to a signal with attenuation. In the open loop transceiver system, a presumption is made that an amount of attenuation in both the outgoing and ingoing directions are equal. In the closed loop transceiver system, a receiver determines an amount of equalization and produces the equalization data to a remote transceiver.

摘要翻译： 用于均衡接收低频和高频测试音的高数据速率串行数据流的电路，精确地测量与低频测试音相关的高频测试音经历的衰减量，并因此产生结果的均衡数据 在相应的均衡或预加重量被加到输出信号上。 然而，更具体地，本发明包括用于均衡或增加具有衰减的信号的预加重的开环和闭环系统。 在开环收发器系统中，假设输出和进入方向上的衰减量相等。 在闭环收发机系统中，接收机确定均衡量，并向远程收发器产生均衡数据。

公开(公告)号：US06297691B1

公开(公告)日：2001-10-02

申请号：US09592464

申请日：2000-06-09

申请人： Stephen D. Anderson ,  Daniel V. Hulse ,  Kevin B. Moore ,  Paul D. Kammann ,  Gabriel A. Maalouf

发明人： Stephen D. Anderson ,  Daniel V. Hulse ,  Kevin B. Moore ,  Paul D. Kammann ,  Gabriel A. Maalouf

IPC分类号： H03D300

CPC分类号： H04L27/2331 ,  H04L27/2273 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0079

摘要： A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals. When the selector disconnects the filter from between the phase detector and the demodulator, the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

摘要翻译： 接收机在非相干FSK和相干8PSK协议中接收调制消息信号。 可选择性地配置的处理器解调消息信号，并且包括基于消息信号导出同相和正交信号的解调器。 相位检测器响应于同相和正交信号以及延迟的同相和正交信号以导出相位信号。 选择器响应于同相和正交信号，以选择性地连接相位检测器和解调器之间的环路滤波器。 当选择器在相位检测器和解调器之间连接滤波器时，解调器响应于滤波的相位信号来锁定消息信号的频率，使得处理器作为锁相环操作以解调相干调制信号。 当选择器从相位检测器和解调器之间断开滤波器时，解调器解调非相干调制信号，相位检测器提供表示解调信号相位斜率的相位信号。