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12 条记录 (耗时 0.016 秒)

    Conversion circuit for process control system
    3.
    发明授权
    Conversion circuit for process control system 失效
    过程控制系统转换电路

    公开(公告)号：US5650777A

    公开(公告)日：1997-07-22

    申请号：US479801

    申请日：1995-06-07

    申请人： Brian L. Westfield ,  Stephen D. Anderson ,  Bennett L. Louwagie ,  Todd A. Piechowski

    发明人： Brian L. Westfield ,  Stephen D. Anderson ,  Bennett L. Louwagie ,  Todd A. Piechowski

    IPC分类号： G05B11/36 ,  G05B19/042 ,  G05B19/418 ,  H04L25/02 ,  G08C19/36

    CPC分类号： G05B19/0423 ,  G05B19/4185 ,  G05B2219/25189 ,  G05B2219/25191 ,  G05B2219/31121 ,  G05B2219/31126 ,  G05B2219/31135 ,  G05B2219/33197 ,  Y02P90/18

    摘要： Conversion circuitry for use in a process control system is adapted for coupling to a primary process control loop. Digital receiver circuitry in the conversion circuitry receives a digital signal transmitted over the primary process control loop from a field transmitter and responsively provides a digital output. A microprocessor receives the digital output and responsively provides a secondary loop control output. Secondary loop control circuitry for coupling to a secondary process control loop receives the secondary loop control output from the microprocessor and responsively controls current flowing through the secondary process control loop. The current flowing through the secondary process control loop is related to the digital signal transmitted by the field transmitter.

    摘要翻译： 用于过程控制系统的转换电路适于耦合到主过程控制回路。 转换电路中的数字接收机电路接收从现场发射机通过主过程控制回路传输的数字信号，并且响应地提供数字输出。 微处理器接收数字输出并且响应地提供辅助回路控制输出。 用于耦合到次级过程控制回路的二次回路控制电路接收来自微处理器的次级回路控制输出，并且响应地控制流过次级过程控制回路的电流。 流过次级过程控制回路的电流与现场发射机发射的数字信号有关。

    Conversion circuit for process control system
    5.
    发明授权
    Conversion circuit for process control system 失效
    过程控制系统转换电路

    公开(公告)号：US06307483B1

    公开(公告)日：2001-10-23

    申请号：US09287775

    申请日：1999-04-07

    申请人： Brian L. Westfield ,  Stephen D. Anderson ,  Bennett L. Louwagie ,  Todd A. Piechowski ,  Gregory C. Brown

    发明人： Brian L. Westfield ,  Stephen D. Anderson ,  Bennett L. Louwagie ,  Todd A. Piechowski ,  Gregory C. Brown

    IPC分类号： G08C1904

    CPC分类号： G05B19/0423 ,  G05B19/4185 ,  G05B2219/25189 ,  G05B2219/25191 ,  G05B2219/31121 ,  G05B2219/31126 ,  G05B2219/31135 ,  G05B2219/33197 ,  Y02P90/18

    摘要： Conversion circuitry for use in a process control system is adapted for coupling to a primary process control loop. Digital receiver circuitry in the conversion circuitry receives a digital signal transmitted over the primary process control loop from a field transmitter and responsively provides a digital output. A microprocessor receives the digital output and responsively provides a secondary loop control output. Secondary loop control circuitry for coupling to a secondary process control loop receives the secondary loop control output from the microprocessor and responsively controls current flowing through the secondary process control loop. The current flowing through the secondary process control loop is related to the digital signal transmitted by the field transmitter.

    摘要翻译： 用于过程控制系统的转换电路适于耦合到主过程控制回路。 转换电路中的数字接收机电路接收从现场发射机通过主过程控制回路传输的数字信号，并且响应地提供数字输出。 微处理器接收数字输出并且响应地提供辅助回路控制输出。 用于耦合到次级过程控制回路的二次回路控制电路接收来自微处理器的次级回路控制输出，并且响应地控制流过次级过程控制回路的电流。 流过次级过程控制回路的电流与现场发射机发射的数字信号有关。

    Bit-edge zero forcing equalizer
    6.
    发明授权
    Bit-edge zero forcing equalizer 有权
    位边缘零强制均衡器

    公开(公告)号：US07653127B2

    公开(公告)日：2010-01-26

    申请号：US10791924

    申请日：2004-03-02

    申请人： Brian T. Brunn ,  Stephen D. Anderson

    发明人： Brian T. Brunn ,  Stephen D. Anderson

    IPC分类号： H03K5/159

    CPC分类号： H04L25/03019 ,  H04L2025/03624

    摘要： Bit-Edge Zero Forcing Equalizer. A novel solution is presented by which a BE-ZFE (Bit-Edge Zero Forcing Equalizer) is employed to drive an error term within a data signal to an essentially zero value. This new BE-ZFE looks at values of data that occur at the bit edges of a data signal and drives the associated error term to zero. The new BE-ZFE is appropriately implemented within communication systems that are phase (or jitter) noise limited. Some examples of such communication systems include high-speed serial links one type of which serviced using a SERDES (Serializer/De-serializer) where data that is originally in a parallel format is serialized into a serial data stream and then subsequently de-serialized back into a parallel data stream.

    摘要翻译： 位边零点强制均衡器。 提出了一种新颖的解决方案，通过该解决方案，使用BE-ZFE（位边缘零强制均衡器）将数据信号内的误差项驱动到基本为零的值。 这个新的BE-ZFE查看发生在数据信号的位边缘的数据的值，并将相关的误差项驱动为零。 在相位（或抖动）噪声限制的通信系统中，新的BE-ZFE被适当地实现。 这种通信系统的一些示例包括使用SERDES（串行器/解串器）服务的一种类型的高速串行链路，其中原始以并行格式的数据被串行化为串行数据流，然后随后被反序列化 并入数据流。

    Receiver operable to receive data at a lower data rate
    8.
    发明授权
    Receiver operable to receive data at a lower data rate 有权
    接收器可操作以以较低的数据速率接收数据

    公开(公告)号：US07532645B1

    公开(公告)日：2009-05-12

    申请号：US11035613

    申请日：2005-01-14

    申请人： Khaldoun Bataineh ,  Stephen D. Anderson ,  Michael Maas ,  David E. Tetzlaff

    发明人： Khaldoun Bataineh ,  Stephen D. Anderson ,  Michael Maas ,  David E. Tetzlaff

    IPC分类号： H04J3/07

    CPC分类号： H04L7/0338

    摘要： A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

    摘要翻译： 一种接收机，包括：过采样模块，其基于所述接收时钟将串行数据流转换为多个过采样数据流; 转移位置模块，其确定过采样数据流和接收时钟的转换位置; 指针调整模块，其基于所述转换位置和所述接收时钟来确定指针变量; 数据选择模块，其基于指针变量确定过采样数据流的等效数据值; 分级寄存器模块，用于从过采样数据流的等效数据值产生偏移数据字和额外的数据字; 以及输出寄存器模块，其从偏移数据字和额外数据字中的至少一个产生并行数据输出。

    Three wire low power transmitter
    9.
    发明授权
    Three wire low power transmitter 失效
    三线低功率发射机

    公开(公告)号：US5245333A

    公开(公告)日：1993-09-14

    申请号：US766667

    申请日：1991-09-25

    申请人： Stephen D. Anderson ,  Roger L. Frick ,  Glen E. Monzo ,  Brian L. Westfield

    发明人： Stephen D. Anderson ,  Roger L. Frick ,  Glen E. Monzo ,  Brian L. Westfield

    IPC分类号： G08C19/02

    CPC分类号： G08C19/02

    摘要： A three wire transmitter bidirectionally communicates AC signals to and from a first external device and sends DC signals to a second external device. The transmitter includes a communication circuit which is energized from power and common terminals and includes memory storage for transmitter status and a process variable (PV). The communication circuit receives a sensor output indicative of the PV and provides the DC signal and the AC signal to a signal terminal which connects to both external devices, and also receives AC signals from the first external device. The communications circuit has a characteristic AC impedance between the signal and common terminals over an AC frequency range for receiving and transmitting AC signals to and from the first external device so that the receiving signals are not shorted out and so the transmitted signals can be received. The communications circuit has a characteristic DC impedance between the signal and common terminals over a range of frequencies which include DC and typically extend to approximately 20 Hz. The characteristic impedance is substantially lower than the impedance of the second external device which receives DC signals so that the accuracy of the DC signal is not compromised.

    摘要翻译： 三线制发射机将交流信号双向地传送到第一外部设备并从第一外部设备传送直流信号到第二外部设备。 发射机包括一个从电源和公共终端通电的通信电路，包括用于发射机状态的存储器和一个过程变量（PV）。 通信电路接收表示PV的传感器输出，并将DC信号和AC信号提供给连接到两个外部设备的信号端子，并且还从第一外部设备接收AC信号。 该通信电路具有在交流频率范围内的信号与公共端之间的特征交流阻抗，用于从第一外部装置接收和发送交流信号，使得接收信号不被短路，因此可以接收所发送的信号。 通信电路在包括DC并且通常延伸到大约20Hz的频率范围内在信号和公共端子之间具有特征的DC阻抗。 特征阻抗基本上低于接收DC信号的第二外部设备的阻抗，使得DC信号的精度不受影响。

    Combined decision feedback equalization and linear equalization
    10.
    发明授权
    Combined decision feedback equalization and linear equalization 有权
    组合决策反馈均衡和线性均衡

    公开(公告)号：US07599431B1

    公开(公告)日：2009-10-06

    申请号：US10997159

    申请日：2004-11-24

    申请人： Stephen D. Anderson ,  Michael A. Nix ,  Brian T. Brunn ,  Jinghui Lu ,  David E. Tetzlaff

    发明人： Stephen D. Anderson ,  Michael A. Nix ,  Brian T. Brunn ,  Jinghui Lu ,  David E. Tetzlaff

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343

    摘要： A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.

    摘要翻译： 通信系统包括发射机，通信信道和接收机。 发射机包括预加重模块，求和模块，线路驱动器和决策反馈预加重（DFP）模块，以基于通信信道响应和符号间干扰产生预先强调的串行数据流 水平。 接收机包括线性均衡器，求和模块，决策模块和判决反馈均衡（DFE）模块。 线性均衡器产生均衡的串行数据流。 求和模块将均衡的串行数据流中的至少一个数据元素与DFE数据元素相加以产生均衡的数据元素。 决策模块解释均衡的数据元素以产生解释的数据元素到DFE模块，其从解释的数据元素产生DFE数据元素。