公开(公告)号：US20050028121A1

公开(公告)日：2005-02-03

申请号：US10632622

申请日：2003-07-31

申请人： Vikram Shrowty ,  Santhanakrishnan Raman

发明人： Vikram Shrowty ,  Santhanakrishnan Raman

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

摘要： A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.

摘要翻译： 公开了一种用于将虚拟金属插入到包括多个对象和时钟网络的电路设计中的方法和系统。 本发明的方面包括识别适合于虚拟金属插入的芯片设计的每个层上的自由空间，其中自由空间被称为虚拟区域。 此后，虚拟区域被优先化，使得与时钟网络相邻的虚拟区域最后填充有虚拟金属。 在优选实施例中，虚拟区域被进一步优先化，使得在与较窄时钟网络相邻的虚拟区域之后，与较宽时钟网络相邻的虚拟区域被虚拟金属填充。