公开(公告)号：US20190252200A1

公开(公告)日：2019-08-15

申请号：US16393339

申请日：2019-04-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ken-Hsien Hsieh ,  Wen-Li Cheng ,  Dong-Yo Jheng ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC分类号： H01L21/308 ,  G06F17/50

CPC分类号： H01L21/3088 ,  G03F1/70 ,  G03F7/70425 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12

摘要： A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.

公开(公告)号：US20190236222A1

公开(公告)日：2019-08-01

申请号：US16225136

申请日：2018-12-19

申请人： Walmart Apollo, LLC

发明人： William Ross Allen ,  Oscar Cantu ,  Richard Montgomery Blair, II

IPC分类号： G06F17/50 ,  G06T19/00 ,  G06N5/04 ,  G06T19/20 ,  G06N5/02 ,  G06F3/0484

CPC分类号： G06F17/5009 ,  G06F3/0484 ,  G06F2217/12 ,  G06N5/025 ,  G06N5/04 ,  G06T19/006 ,  G06T19/20 ,  G06T2210/16

摘要： Examples provide a system and method for augmented apparel design. Sensor data generated by a set of sensor devices attached to at least one moveable member of a mannequin in a selected configuration is analyzes to generate motion data. The motion data is analyzed with design data associate with a garment design to generate an augmented reality (AR) overlay including an AR image of an item of clothing conforming to the garment design. The AR overlay is superimposed over a real-world image of a portion of the mannequin to generate an AR display of the item of clothing on the mannequin. As one or more design elements are altered and/or member(s) of the mannequin move, an AR generator updates the design overlay to reflect predicted changes to the garment in response to the changes. The system outputs response data identifying fabric stress points and/or recommended design changes.

公开(公告)号：US20190210287A1

公开(公告)日：2019-07-11

申请号：US16352269

申请日：2019-03-13

申请人： Stratasys, Inc.

发明人： Clint Newell

IPC分类号： B29C64/379 ,  B29C64/295 ,  B29C64/245 ,  G06F17/50

CPC分类号： B29C64/30 ,  B29C64/106 ,  B29C64/118 ,  B29C64/227 ,  B29C64/245 ,  B29C64/295 ,  B29C64/379 ,  B29K2995/0039 ,  B29K2995/004 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y70/00 ,  G06F17/50 ,  G06F2217/12

摘要： A method of printing a hollow part with a robotic additive manufacturing system includes extruding thermoplastic material onto a build platform movable in at least two degrees of freedom in a helical pattern along a continuous 3D tool path with an extruder mounted on a robotic arm, to thereby print a hollow member having a length and a diameter. The method includes orienting the hollow member during printing by moving the build platform based on a geometry of the hollow member wherein the movement of the build platform and the movement of the robotic arm are synchronized to print the part without support structures.

公开(公告)号：US20190197213A1

公开(公告)日：2019-06-27

申请号：US15853311

申请日：2017-12-22

申请人： D2S, Inc.

发明人： P. Jeffrey Ungar

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12

摘要： Methods for reticle enhancement technology (RET) include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array, which is an array of function values. A continuous tone mask (CTM) is provided, where the CTM is used to produce the predicted wafer pattern. Methods for RET also include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.

公开(公告)号：US20190172798A1

公开(公告)日：2019-06-06

申请号：US16271062

申请日：2019-02-08

申请人： International Business Machines Corporation

发明人： Kafai Lai ,  Rasit O Topaloglu

IPC分类号： H01L23/00 ,  H01L21/67 ,  H01L23/544

CPC分类号： H01L23/573 ,  B65D33/16 ,  B65D33/28 ,  G06F17/5072 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06F2217/64 ,  G06F2217/66 ,  H01L21/67282 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54433 ,  H03K19/195

摘要： Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

公开(公告)号：US20190171789A1

公开(公告)日：2019-06-06

申请号：US16272391

申请日：2019-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chung-Yun CHENG ,  Chin-Chang HSU ,  Hsien-Hsin Sean LEE ,  Jian-Yi LI ,  Li-Sheng KE ,  Wen-Ju YANG

IPC分类号： G06F17/50 ,  G03F1/70

CPC分类号： G06F17/5081 ,  G03F1/70 ,  G06F17/5072 ,  G06F2217/12

摘要： A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.

公开(公告)号：US20190131290A1

公开(公告)日：2019-05-02

申请号：US15797842

申请日：2017-10-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC分类号： H01L27/02 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/12 ,  H01L27/0203

摘要： A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.

公开(公告)号：US20190095573A1

公开(公告)日：2019-03-28

申请号：US15878009

申请日：2018-01-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Hsiang HUANG ,  Sheng-Hsiung CHEN ,  Fong-Yuan CHANG

IPC分类号： G06F17/50 ,  G03F1/36 ,  H01L27/02

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

摘要： A method of generating a layout of an IC includes identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell, and determining whether or not the target pin is capable of being extended into the second cell. Based on a determination that the target pin is capable of being extended into the second cell, the target pin is modified to include an extension into the second cell, the target pin thereby crossing the shared boundary. At least one of the identifying, determining, or modifying is executed by a processor of a computer.

公开(公告)号：US20190095551A1

公开(公告)日：2019-03-28

申请号：US15816210

申请日：2017-11-17

申请人： International Business Machines Corporation

发明人： Dureseti Chidambarrao ,  Jason D. Hibbeler ,  Dongbing Shao ,  Steven Zebertavage

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/10 ,  G06F2217/12 ,  H01L27/0207

摘要： A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

公开(公告)号：US20190072845A1

公开(公告)日：2019-03-07

申请号：US15696505

申请日：2017-09-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

发明人： CHIEH-YU LIN ,  DONGBING SHAO ,  KEHAN TIAN ,  ZHENG XU

IPC分类号： G03F1/36 ,  G06F17/50 ,  G03F1/70

CPC分类号： G03F1/36 ,  G03F1/38 ,  G03F1/70 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12

摘要： Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.