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公开(公告)号：US20060026551A1
公开(公告)日：2006-02-02
申请号：US10903836
申请日：2004-07-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.
摘要翻译： 通过将大于预定大小的设计中的每个块划分成矩形网格，为集成电路设计生成密度抽象视图; 计算网格中每个矩形中金属面积的总和; 在具有等于矩形的金属面积和的面积的每个矩形中创建对象; 并将块中所有创建的对象存储为视图。 视图可以与集成电路设计的任何其他视图一起存储在布局数据库中，然后用于通过将与块重叠的密度视图中的方形对象的面积相加来确定与块重叠的块的密度 到瓷砖。
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2.发明授权公开(公告)号：US07007259B2
公开(公告)日：2006-02-28
申请号：US10632622
申请日：2003-07-31
CPC分类号： G06F17/5068 , G06F2217/12 , G06F2217/62 , Y02P90/265
摘要： A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.
摘要翻译： 公开了一种用于将虚拟金属插入到包括多个对象和时钟网络的电路设计中的方法和系统。 本发明的方面包括识别适合于虚拟金属插入的芯片设计的每个层上的自由空间，其中自由空间被称为虚拟区域。 此后，虚拟区域被优先化，使得与时钟网络相邻的虚拟区域最后填充有虚拟金属。 在优选实施例中，虚拟区域被进一步优先化，使得在与较窄时钟网络相邻的虚拟区域之后，与较宽时钟网络相邻的虚拟区域被虚拟金属填充。
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公开(公告)号：US07174526B2
公开(公告)日：2007-02-06
申请号：US10903836
申请日：2004-07-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.
摘要翻译： 通过将大于预定大小的设计中的每个块划分成矩形网格，为集成电路设计生成密度抽象视图; 计算网格中每个矩形中金属面积的总和; 在具有等于矩形的金属面积和的面积的每个矩形中创建对象; 并将块中所有创建的对象存储为视图。 视图可以与集成电路设计的任何其他视图一起存储在布局数据库中，然后用于通过将与块重叠的密度视图中的方形对象的面积相加来确定与块重叠的块的密度 到瓷砖。
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4.发明申请公开(公告)号：US20050028121A1
公开(公告)日：2005-02-03
申请号：US10632622
申请日：2003-07-31
CPC分类号： G06F17/5068 , G06F2217/12 , G06F2217/62 , Y02P90/265
摘要： A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.
摘要翻译： 公开了一种用于将虚拟金属插入到包括多个对象和时钟网络的电路设计中的方法和系统。 本发明的方面包括识别适合于虚拟金属插入的芯片设计的每个层上的自由空间，其中自由空间被称为虚拟区域。 此后，虚拟区域被优先化，使得与时钟网络相邻的虚拟区域最后填充有虚拟金属。 在优选实施例中，虚拟区域被进一步优先化，使得在与较窄时钟网络相邻的虚拟区域之后，与较宽时钟网络相邻的虚拟区域被虚拟金属填充。
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公开(公告)号：US06757883B1
公开(公告)日：2004-06-29
申请号：US10316594
申请日：2002-12-11
申请人： Vikram Shrowty , Santhanakris Raman
发明人： Vikram Shrowty , Santhanakris Raman
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G06F17/5068
摘要： Free space on a routed IC is estimated using expanding hierarchical search quadtrees or octrees. Nodes defining rectangular spaces of a layer are created in the tree. Definitions of polygons representing occupied space in the rectangular space are subtracted from a free-space polygon based on the rectangular space. A cost factor is identified for the node, and the process repeats with additional feature polygons until either the cost factor exceeds a maximum or no further feature polygons exist in the layer. If the cost factor exceeds the limit, the node is fractured into child nodes, each defining a quadrant of the parent rectangular space and each containing polygon definitions from the parent node. The process repeats until either the cost factor for each node is not greater than the limit or a dimension of the rectangular space of the node reaches a selected minimum. The nodes define free spaces, which are summed to identify the free space on the IC layer.
摘要翻译： 使用扩展分层搜索四叉树或八进制估计路由IC上的空闲空间。 在树中创建定义层的矩形空间的节点。 基于矩形空间从空间多边形中减去表示矩形空间中占用空间的多边形的定义。 为节点识别成本因素，并且该过程使用附加的特征多边形重复，直到成本因子超过最大值或者该层中不存在进一步的特征多边形。 如果成本因子超过限制，则节点被分解为子节点，每个节点定义父矩形空间的象限，每个子节点包含来自父节点的多边形定义。 该过程重复，直到每个节点的成本因子不大于极限或节点的矩形空间的尺寸达到所选择的最小值。 节点定义自由空间，它们相加以识别IC层上的自由空间。
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公开(公告)号：US07260803B2
公开(公告)日：2007-08-21
申请号：US10683369
申请日：2003-10-10
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.
摘要翻译： 公开了一种用于在集成电路的设计数据中执行虚拟金属插入的方法和系统，其中设计数据包括由虚拟填充工具插入的虚拟金属物体。 在设计数据的一部分改变之后，执行检查以确定任何虚拟金属物体是否与设计数据中的任何其他对象相交。 如果是这样，则从设计数据中删除相交的虚拟金属物体，从而避免重新运行虚拟填充工具。
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公开(公告)号：US09691027B1
公开(公告)日：2017-06-27
申请号：US13324987
申请日：2011-12-13
CPC分类号： G06N5/025 , G06F17/30082 , G06F17/30126 , G06F17/30144 , G06F21/556 , G06F21/577 , G06F21/604 , G06F21/6245 , G06F2221/034 , G06F2221/2101 , H04L41/0604 , H04L63/20
摘要： Machine-learning based detection (MLD) profiles can be used to identify sensitive information in documents. The MLD profile can be used to generate a confidence value for the document that expresses the degree of confidence with which the MLD profile can classify the document as sensitive or not. In one embodiment, a data loss prevention system provides or suggests a confidence level threshold to a user of the data loss prevention system by providing a confidence level threshold for the MLD profile to the user, the confidence level threshold to be used as the boundary between sensitive data and non-sensitive data. In one embodiment the provided confidence level threshold is determined by scanning a random data set using the MLD profile.
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公开(公告)号：US07237218B2
公开(公告)日：2007-06-26
申请号：US10927919
申请日：2004-08-26
申请人： Vikram Shrowty , Santhanakris Raman
发明人： Vikram Shrowty , Santhanakris Raman
IPC分类号： G06F17/50
CPC分类号： H01L27/105 , G11C5/063 , G11C5/14 , H01L23/522 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.
摘要翻译： 本发明优化了集成电路（IC）芯片的动态功率特性。 IC芯片包括多个层，其中至少一个层是向IC芯片提供电力的功率网格层，并且包括地（Vss）网。 该方法包括提供至少一个虚拟金属网格层，并将虚拟金属网格层耦合到功率网格层上的Vss网络，从而增加Vss网络上的电容。
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公开(公告)号：US20060046353A1
公开(公告)日：2006-03-02
申请号：US10927919
申请日：2004-08-26
申请人： Vikram Shrowty , Santhanakris Raman
发明人： Vikram Shrowty , Santhanakris Raman
IPC分类号： H01L21/82
CPC分类号： H01L27/105 , G11C5/063 , G11C5/14 , H01L23/522 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.
摘要翻译： 本发明优化了集成电路（IC）芯片的动态功率特性。 IC芯片包括多个层，其中至少一个层是向IC芯片提供电力的功率网格层，并且包括地（Vss）网。 该方法包括提供至少一个虚拟金属网格层，并将虚拟金属网格层耦合到功率网格层上的Vss网络，从而增加Vss网络上的电容。
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10.发明授权Time and space efficient method and system for detecting structured data in free text 有权时间和空间有效的方法和系统，用于检测自由文本中的结构化数据公开(公告)号：US08949371B1
公开(公告)日：2015-02-03
申请号：US13249108
申请日：2011-09-29
申请人： Vikram Shrowty
发明人： Vikram Shrowty
CPC分类号： G06F21/6218
摘要： A server system identifies structured data for protection and creates an index of the structured data, the index comprising a set of Bloom filters. The server system distributes the index to an endpoint device to enable the endpoint device to monitor for structured data occurring in free text data associated with the endpoint device. The endpoint device may load, from the index file, a set of Bloom filters into memory and identify free text data for monitoring. The endpoint device may then determine whether the free text data contains at least a portion of the structured data using the set of Bloom filters.
摘要翻译： 服务器系统识别用于保护的结构化数据并创建结构化数据的索引，索引包括一组布隆过滤器。 服务器系统将索引分发到端点设备，以使端点设备能够监视与端点设备相关联的自由文本数据中发生的结构化数据。 端点设备可以从索引文件将一组Bloom过滤器加载到存储器中，并识别用于监视的自由文本数据。 然后，终端设备可以使用一组布隆过滤器来确定自由文本数据是否包含结构化数据的至少一部分。
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