公开(公告)号：US08174290B2

公开(公告)日：2012-05-08

申请号：US12912348

申请日：2010-10-26

申请人： Yuki Higuchi

发明人： Yuki Higuchi

IPC分类号： G01R29/02 ,  H03B1/00

CPC分类号： H03K5/1252

摘要： A noise reduction circuit includes first and second reset signal generation circuits that generate first and second reset signals that are activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high level or a low level is maintained, and first and second counter circuits that count an inverted signal of the clock signal, and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit that includes a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock, wherein the selector circuit selects and outputs any of: a signal fixed at a high level or a low level, and an output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

摘要翻译： 噪声降低电路包括产生第一和第二复位信号的第一和第二复位信号产生电路，当第一和第二复位信号在数据输入信号变为低电平或高电平时被激活，并且当高电平或高电平时与时钟信号同步地停用 保持低电平，第一和第二计数器电路对时钟信号的反相信号进行计数，并由第一或第二复位信号复位。 噪声降低电路还包括数据输出电路，其包括选择器电路和输出触发器电路，输出触发电路与时钟同步地输出由选择器电路选择的信号，其中选择器电路选择并输出以下信号：固定信号 根据第一和第二计数器电路的输出信号的逻辑电平，输出触发电路的输出信号为高电平或低电平。