Resist hardening and development processes for semiconductor device manufacturing
    11.
    发明授权
    Resist hardening and development processes for semiconductor device manufacturing 有权
    半导体器件制造的抗硬化和开发工艺

    公开(公告)号:US09411237B2

    公开(公告)日:2016-08-09

    申请号:US14205324

    申请日:2014-03-11

    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

    Abstract translation: 在一些实施例中,提供了在衬底上形成蚀刻掩模的方法,其包括(1)在衬底上形成抗蚀剂层; (2)将抗蚀剂层的一个或多个区域暴露于能量源,以便改变暴露区域的物理性质和化学性质中的至少一个; (3)对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性,硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积(ALD)室; 和(4)干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

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