公开(公告)号：US20240363755A1

公开(公告)日：2024-10-31

申请号：US18531497

申请日：2023-12-06

申请人： Adeia Semiconductor Solutions LLC

发明人： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC分类号： H01L29/78 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

摘要： A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

公开(公告)号：US20240363425A1

公开(公告)日：2024-10-31

申请号：US18769679

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L21/823462 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66795 ,  H01L27/088

摘要： The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20240363312A1

公开(公告)日：2024-10-31

申请号：US18768190

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Cheng Kuang Tso ,  Chou-Feng Lee ,  Chih-Hsien Hsu ,  Chung-Hsiu Cheng ,  Jr-Sheng Chen

IPC分类号： H01J37/32 ,  H01L21/3065

CPC分类号： H01J37/32449 ,  H01J37/32522 ,  H01L21/3065 ,  H01J2237/334

摘要： Methods and systems for uniformly cooling a dome within a plasma treatment system are disclosed. The methods and systems utilize a diffuser including a perforated plate and a cone. The perforated plate includes a center portion and multiple arrays of holes with each array being located circumferentially at a different distance from the center. The cone extends away from the center. The diffuser spreads cooling gas more uniformly across the surface of the dome.

公开(公告)号：US20240355700A1

公开(公告)日：2024-10-24

申请号：US18458367

申请日：2023-08-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Siraj Akhtar ,  Enis Tuncer ,  Hiep Xuan Nguyen

IPC分类号： H01L23/367 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/00

CPC分类号： H01L23/367 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16059 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/182

摘要： The present disclosure generally relates to die-package interconnect in a semiconductor device assembly to facilitate thermal conduction. In an example, a semiconductor device assembly includes a semiconductor substrate, a metallization structure, a package substrate, a die-package interconnect, and one or more insulation layers. The metallization structure is on the semiconductor substrate and includes a first metal layer. The die-package interconnect is between the metallization structure and a second metal layer of the package substrate. The die-package interconnect overlaps at least part of a transistor on the semiconductor substrate. The insulation layer(s) are on the metallization structure and have a first portion having a first thickness and a second portion having a second thickness. The first portion is outside a footprint of the transistor. The second portion is between the die-package interconnect and the at least part of the transistor. The first thickness being larger than the second thickness.

公开(公告)号：US12125708B2

公开(公告)日：2024-10-22

申请号：US17276982

申请日：2020-04-10

申请人： Hitachi High-Tech Corporation

发明人： Takashi Hattori ,  Yu Zhao ,  Hiroyuki Kobayashi ,  Hiroto Otake

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67

CPC分类号： H01L21/31116 ,  H01L21/02164 ,  H01L21/3065 ,  H01L21/67115

摘要： Provided is an etching method for etching a silicon oxide film with a high accuracy at a high selection ratio with respect to a silicon nitride film, the etching method of etching a film structure, in which an end portion of a film layer in which the silicon oxide film and the silicon nitride film formed in advance on a wafer disposed in a processing chamber are alternately stacked in a vertical direction forms a side wall of a groove or a hole, by supplying processing gas into the processing chamber includes a step of supplying hydrogen fluoride and alcohol vapor into the processing chamber, maintaining the wafer at a temperature of −20° C. or lower, preferably −20° C. to −60° C., and etching the silicon oxide film from the end portion in a lateral direction.

公开(公告)号：US12119206B2

公开(公告)日：2024-10-15

申请号：US18133356

申请日：2023-04-11

申请人： ASM AMERICA, INC.

发明人： Anton Mavretic ,  Ian M. Costanzo ,  Ronald Anthony Decker

IPC分类号： H03F3/191 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861 ,  H01L49/02 ,  H02M3/335 ,  H03H7/38 ,  H03H7/40 ,  H03K17/687 ,  H04B1/44 ,  H02M3/00 ,  H03K17/10 ,  H03K17/691 ,  H03K17/795

CPC分类号： H01J37/32082 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L28/20 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/861 ,  H02M3/33569 ,  H03H7/38 ,  H03H7/40 ,  H03K17/687 ,  H04B1/44 ,  H01J2237/334 ,  H02M3/01 ,  H03F3/191 ,  H03K17/102 ,  H03K2017/6875 ,  H03K17/691 ,  H03K17/7955

摘要： In one embodiment, an impedance matching network includes a variable reactance circuit having fixed reactance components and corresponding switching circuits. Each switching circuit includes a diode and a driver circuit. The driver circuit includes, coupled in series, a biasing current source positioned to provide a bias current to bias the diode, a first switch, a second switch, and a resistor. For each diode of each switching circuit, the control circuit is configured to receive a value related to a voltage drop on the resistor and, based on the value related to the voltage drop, adjust the bias current being provided by the biasing current source.

公开(公告)号：US12112941B2

公开(公告)日：2024-10-08

申请号：US17764223

申请日：2020-08-31

申请人： THE INDUSTRY & ACADEMIC COOPERPATION IN CHUNGNAM NATIONAL UNIVERSITY (IAC)

发明人： Seong Min Kang ,  Ji Seong Choi

IPC分类号： H01L21/02 ,  B01L3/00 ,  C23C16/40 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC分类号： H01L21/0212 ,  B01L3/502707 ,  B01L3/502746 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32137 ,  B01L2300/12 ,  B01L2300/166 ,  B01L2400/088

摘要： A selective liquid sliding surface includes: a base layer; multiple pillars protruding from the base layer; and a head protruding from an upper surface of each of the multiple pillars and having a larger cross-sectional diameter than the pillar, wherein the head includes a first head protruding from the pillar and a second head protruding from a periphery of the first head, and the base layer, the pillar, and the head are formed of the same material.

公开(公告)号：US20240332039A1

公开(公告)日：2024-10-03

申请号：US18589252

申请日：2024-02-27

申请人： ASM IP Holding B.V.

发明人： Tom E. Blomberg ,  Varun Sharma

IPC分类号： H01L21/67 ,  C23C16/44 ,  C23C16/455 ,  H01J37/32 ,  H01L21/3065

CPC分类号： H01L21/67063 ,  C23C16/4412 ,  C23C16/45559 ,  H01J37/3244 ,  H01L21/3065

摘要： To create constant partial pressures of the by-products and residence time of the gas molecules across the wafer, a dual showerhead reactor can be used. A dual showerhead structure can achieve spatially uniform partial pressures, residence times and temperatures for the etchant and for the by-products, thus leading to uniform etch rates across the wafer. The system can include differential pumping to the reactor.

公开(公告)号：US20240331986A1

公开(公告)日：2024-10-03

申请号：US18616526

申请日：2024-03-26

申请人： Tokyo Electron Limited

发明人： Yasunobu SUZUKI

IPC分类号： H01J37/32 ,  H01L21/3065

CPC分类号： H01J37/32715 ,  H01L21/3065 ,  H01J2237/20207 ,  H01J2237/334

摘要： A plasma etching apparatus includes: a chamber, a support body provided inside the chamber to hold a substrate, a plasma generator provided with a plasma source to generate plasma, and a controller. The support body has a placement surface on which the substrate is placed, rotates the substrate about a perpendicular line passing through a center of the substrate, and is configured such that the placement surface is tilted with respect to a horizontal plane and the perpendicular line passes through a center of the plasma source only when the placement surface is not tilted with respect to the horizontal plane. The controller performs control so that during plasma etching, the placement surface is tilted with respect to the horizontal plane and the substrate is rotated about the perpendicular line, and control so that a total number of rotations of the substrate about the perpendicular line becomes a predetermined value.

公开(公告)号：US20240331974A1

公开(公告)日：2024-10-03

申请号：US18625592

申请日：2024-04-03

申请人： HITACHI HIGH-TECH CORPORATION

发明人： Isao MORI ,  Masaru Izawa ,  Naoki Yasui ,  Norihiko Ikeda ,  Kazuya Yamada

IPC分类号： H01J37/32 ,  H01L21/3065 ,  H05H1/46

CPC分类号： H01J37/32128 ,  H01J37/32183 ,  H01J37/32577 ,  H01L21/3065 ,  H05H1/46 ,  H01J2237/334

摘要： A plasma processing apparatus includes a processing chamber in which a sample is subjected to plasma processing, a first radio frequency power supply that supplies radio frequency power for generating plasma, a sample stage on which the sample is mounted, and a second radio frequency power supply that supplies radio frequency power to the sample stage, the plasma processing apparatus further includes a DC power supply that applies a DC voltage, that is changed according to a periodically repeated waveform, to the sample stage, and the waveform of one cycle has a period in which amplitude changes by a predetermined amount or more during a predetermined time. Accordingly, charged particles on a wafer surface are removed, a trench shape with high verticality can be obtained, and damage to a film that is not to be etched inside a trench can be reduced.