公开(公告)号：US10909045B2

公开(公告)日：2021-02-02

申请号：US16228042

申请日：2018-12-20

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Reiley Jeyapaul ,  Roxana Rusitoru

IPC: G06F12/14 ,  G06F12/10

Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.

公开(公告)号：US20200371913A1

公开(公告)日：2020-11-26

申请号：US16418346

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Pavel Shamis

IPC: G06F12/0804

Abstract: A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.

公开(公告)号：US10324727B2

公开(公告)日：2019-06-18

申请号：US15238778

申请日：2016-08-17

Applicant: ARM LIMITED

Inventor： Curtis Glenn Dunham ,  Mitchell Bryan Hayenga

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus executes a stream of instructions. Memory access circuitry accesses a memory in response to control signals associated with a memory access instruction that is executed in the stream of instructions. Branch prediction circuitry predicts the outcome of branch instructions in the stream of instructions based on a branch prediction table. Processing circuitry performs a determination of whether out-of-order execution of memory access instructions is to be performed based on memory prediction data, and selectively enables out-of-order execution of the memory access instructions in dependence on the determination. The memory prediction data is stored in the branch prediction table.

公开(公告)号：US11960945B2

公开(公告)日：2024-04-16

申请号：US17225674

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Andreas Lars Sandberg ,  Roxana Rusitoru

IPC: G06F9/46 ,  G06F9/54 ,  G06F12/02 ,  G06F12/1009 ,  G06F15/78

CPC classification number: G06F9/546 ,  G06F9/542 ,  G06F12/023 ,  G06F12/1009 ,  G06F15/7817

Abstract: Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.

公开(公告)号：US11409530B2

公开(公告)日：2022-08-09

申请号：US16103995

申请日：2018-08-16

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Pavel Shamis ,  Jamshed Jalal ,  Michael Filippo

IPC: G06F15/00 ,  G06F9/30

Abstract: A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.

公开(公告)号：US11176042B2

公开(公告)日：2021-11-16

申请号：US16418380

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Pavel Shamis ,  Eric Ola Harald Liljedahl

IPC: G06F12/0815 ,  G06F12/10 ,  G06F11/34 ,  G06F11/30

Abstract: A method and apparatus for monitoring cache transactions in a cache of a data processing system is provided. Responsive to a cache transaction associated with a transaction address, when a cache controller determines that the cache transaction is selected for monitoring, the cache controller retrieves a pointer stored in a register, determines a location in a log memory from the pointer, and writes a transaction identifier to the determined location in the log memory. The transaction identifier is associated with the transaction address and may be a virtual address, for example. The pointer is updated and stored to the register. The architect of the apparatus may include a mechanism for atomically combining data access instructions with an instruction to commence monitoring.

公开(公告)号：US10725992B2

公开(公告)日：2020-07-28

申请号：US16207241

申请日：2018-12-03

Applicant: ARM LIMITED

Inventor： Mitchell Bryan Hayenga ,  Curtis Glenn Dunham ,  Dam Sunwoo

IPC: G06F16/22 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F16/172 ,  G06F21/75

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

公开(公告)号：US10423446B2

公开(公告)日：2019-09-24

申请号：US15361871

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Roxana Rusitoru

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/0815 ,  G06F9/46 ,  G06F9/54

Abstract: Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configured to modify one or more of the attributes corresponding to that program task in response to execution of that program task.