公开(公告)号：US11314648B2

公开(公告)日：2022-04-26

申请号：US15427421

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Kias Magnus Bruce ,  Alex James Waugh ,  Geoffray Lacourba ,  Paul Gilbert Meyer ,  Bruce James Mathewson ,  Phanindra Kumar Mannava

IPC: G06F12/0862 ,  G06F12/0831 ,  G06F12/0811 ,  G06F15/78 ,  G06F11/34

Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

公开(公告)号：US10552338B2

公开(公告)日：2020-02-04

申请号：US15437581

申请日：2017-02-21

Applicant: ARM Limited

Inventor： Abhishek Raja ,  Michael Filippo

IPC: G06F12/1027 ,  G06F12/0864 ,  G06F12/1009

Abstract: An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each item of address translation data has a page size indication for a page within the memory system that is associated with that address translation data. Allocation circuitry performs an allocation process to determine the address translation data to be stored in each entry. Further, mode control circuitry is used to switch a mode of operation of the apparatus between a non-skewed mode and at least one skewed mode, dependent on a page size analysis operation. The address translation cache is organised as a plurality of portions, and in the non-skewed mode the allocation circuitry is arranged, when performing the allocation process, to permit the address translation data to be allocated to any of the plurality of portions. In contrast, when in the at least one skewed mode, the allocation circuitry is arranged to reserve at least one portion for allocation of address translation data associated with pages of a first page size and at least one other portion for allocation of address translation data associated with pages of a second page size different to the first page size.

公开(公告)号：US10402349B2

公开(公告)日：2019-09-03

申请号：US15427391

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US11409530B2

公开(公告)日：2022-08-09

申请号：US16103995

申请日：2018-08-16

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Pavel Shamis ,  Jamshed Jalal ,  Michael Filippo

IPC: G06F15/00 ,  G06F9/30

Abstract: A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.

公开(公告)号：US10983916B2

公开(公告)日：2021-04-20

申请号：US15446235

申请日：2017-03-01

Applicant: ARM Limited

Inventor： Huzefa Moiz Sanjeliwala ,  Klas Magnus Bruce ,  Leigang Kou ,  Michael Filippo ,  Miles Robert Dooley ,  Matthew Andrew Rafacz

IPC: G06F12/00 ,  G06F12/0897 ,  G06F12/0862

Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.

公开(公告)号：US10545877B2

公开(公告)日：2020-01-28

申请号：US15945900

申请日：2018-04-05

Applicant: Arm Limited

Inventor： Abhishek Raja ,  Michael Filippo

IPC: G06F12/00 ,  G06F12/1027

Abstract: An apparatus and method are provided for accessing an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. The virtual address is generated from a plurality of source values. Allocation circuitry is responsive to received address translation data, to allocate an entry within the address translation cache to store the received address translation data. A hash value indication is associated with the allocated entry, where the hash value indication is computed from the plurality of source values used to generate a virtual address associated with the received address translation data. Lookup circuitry is responsive to an access request associated with a target virtual address, to perform a lookup process employing a target hash value computed from the plurality of source values used to generate the target virtual address, in order to identify any candidate matching entry in the address translation cache. When there is at least one candidate matching entry, a virtual address check process is then performed in order to determine whether any candidate matching entry is an actual matching entry whose address translation data enables the target virtual address to be translated to a corresponding target physical address. Such an approach can significantly improve the performance of accesses to the address translation cache, and can also give rise to power consumption savings.

公开(公告)号：US10572259B2

公开(公告)日：2020-02-25

申请号：US15876430

申请日：2018-01-22

Applicant: Arm Limited

Inventor： Jesse Garrett Beu ,  Alejandro Rico Carro ,  Lee Evan Eisen ,  Michael Filippo

IPC: G06F9/30 ,  G06F12/0875

Abstract: An apparatus and method of operating a data processing apparatus are provided. The data processing circuitry is responsive to a hint instruction to then assert at least one performance modifying control signal, when subsequently generating control signals for other data processing instructions. This causes the data processing functional hardware which performs the data processing operations defined by the data processing instructions to operate in a modified manner, although the data processing results produced do not change in dependence on whether the at least one performance modifying control signal is asserted.

公开(公告)号：US10229066B2

公开(公告)日：2019-03-12

申请号：US15281502

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Miles Robert Dooley ,  Matthew Andrew Rafacz ,  Huzefa Moiz Sanjeliwala ,  Michael Filippo

IPC: G06F12/08 ,  G06F12/1045 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/30

Abstract: A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. When a current capacity of the resolution circuitry is below the resolution circuitry limit, the resolution circuitry acquires the request for data by receiving the request for data from the queue circuitry, stores the request for data in association with the storage location, issues the request for data, and causes a result of issuing the request for data to be provided to said storage location. When the current capacity of the resolution circuitry meets or exceeds the resolution circuitry limit, the resolution circuitry acquires the request for data by examining a next request for data in the queue circuitry and issues a further request for the data based on the request for data.

公开(公告)号：US10176104B2

公开(公告)日：2019-01-08

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu Kudaravalli ,  Matthew Paul Elwood ,  Adam George ,  Muhammad Umar Farooq ,  Michael Filippo

IPC: G06F9/40 ,  G06F9/45 ,  G06F12/02 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/30 ,  G06F8/41

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.

公开(公告)号：US10140216B2

公开(公告)日：2018-11-27

申请号：US15002648

申请日：2016-01-21

Applicant: ARM LIMITED

Inventor： Michael John Williams ,  Michael Filippo ,  Hazim Shafi

IPC: G06F12/10 ,  G06F12/1027 ,  G06F3/06 ,  G06F12/1009 ,  G06F11/34

Abstract: An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction.