公开(公告)号：US11445020B2

公开(公告)日：2022-09-13

申请号：US16828207

申请日：2020-03-24

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Jamshed Jalal ,  Curtis Glenn Dunham ,  Roxana Rusitoru

IPC: G06F11/07 ,  H04L67/1095 ,  G06F11/14 ,  G06F11/30 ,  G06F15/78 ,  G06F12/0808 ,  G06F12/0815

Abstract: Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition and being a request that the copy of the given data item is written to a destination node of the data handling nodes; and the target node is configured, in response to the conditional request: (i) when the outcome of the execution condition is successful, to write the data item to the destination node and to communicate a completion-success indicator to the requesting node; and (ii) when the outcome of the execution condition is a failure, to communicate a completion-failure indicator to the requesting node.

公开(公告)号：US10552212B2

公开(公告)日：2020-02-04

申请号：US15361819

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Roxana Rusitoru

IPC: G06F9/48 ,  G06F9/46

Abstract: Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.

公开(公告)号：US11934272B2

公开(公告)日：2024-03-19

申请号：US17742875

申请日：2022-05-12

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard ,  Kar-Lik Kasim Wong

IPC: G06F11/14

CPC classification number: G06F11/1407

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

公开(公告)号：US10671426B2

公开(公告)日：2020-06-02

申请号：US15361770

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Roxana Rusitoru

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F12/0831 ,  G06F13/16 ,  G06F9/52

Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.

公开(公告)号：US10534719B2

公开(公告)日：2020-01-14

申请号：US15819328

申请日：2017-11-21

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Roxana Rusitoru ,  Curtis Glenn Dunham

IPC: G06F12/1009 ,  G06F12/0802 ,  G06F12/06 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1036

Abstract: A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.

公开(公告)号：US10909045B2

公开(公告)日：2021-02-02

申请号：US16228042

申请日：2018-12-20

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Reiley Jeyapaul ,  Roxana Rusitoru

IPC: G06F12/14 ,  G06F12/10

Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.

公开(公告)号：US10884850B2

公开(公告)日：2021-01-05

申请号：US16043975

申请日：2018-07-24

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G06F11/20 ,  G06F12/02 ,  G11C29/00

Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.

公开(公告)号：US11550585B2

公开(公告)日：2023-01-10

申请号：US17209606

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Roxana Rusitoru ,  Jonathan Curtis Beard ,  Alexander Sebastian Bischoff

IPC: G06F9/34 ,  G06F12/10 ,  G06F9/30

Abstract: A method and apparatus is provided for processing accelerator instructions in a data processing apparatus, where a block of one or more accelerator instructions is executable on a host processor or on an accelerator device. For an instruction executed on the host processor and referencing a first virtual address, the instruction is issued to an instruction queue of the host processor and executed the instruction by the host processor, the executing including translating, by translation hardware of the host processor, the first virtual address to a first physical address. For an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated, by the translation hardware, to a second physical address and the instruction is sent to the accelerator device referencing the second physical address. An accelerator task may be initiated by writing configuration data to an accelerator job queue.

公开(公告)号：US20220308879A1

公开(公告)日：2022-09-29

申请号：US17209606

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Roxana Rusitoru ,  Jonathan Curtis Beard ,  Alexander Sebastian Bischoff

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/10

Abstract: A method and apparatus is provided for processing accelerator instructions in a data processing apparatus, where a block of one or more accelerator instructions is executable on a host processor or on an accelerator device. For an instruction executed on the host processor and referencing a first virtual address, the instruction is issued to an instruction queue of the host processor and executed the instruction by the host processor, the executing including translating, by translation hardware of the host processor, the first virtual address to a first physical address. For an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated, by the translation hardware, to a second physical address and the instruction is sent to the accelerator device referencing the second physical address. An accelerator task may be initiated by writing configuration data to an accelerator job queue.

公开(公告)号：US20190018787A1

公开(公告)日：2019-01-17

申请号：US15819574

申请日：2017-11-21

Applicant: Arm Limited

Inventor： Roxana Rusitoru ,  Jonathan Curtis Beard ,  Curtis Glenn Dunham

IPC: G06F12/1009 ,  G06F9/455

Abstract: A host machine uses a range-based address translation system rather than a conventional page-based system. This enables address translation to be performed with improved efficiency, particularly when nest virtual machines are used. A data processing system utilizes range-based address translation to provide fast address translation for virtual machines that use virtual address space.