公开(公告)号：US20180218107A1

公开(公告)日：2018-08-02

申请号：US15418602

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Karen Lee Delk ,  Marlin Wayne Frederick, JR. ,  Ravindra Narayana Rao

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/78

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.

公开(公告)号：US09653413B2

公开(公告)日：2017-05-16

申请号：US14307574

申请日：2014-06-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk

IPC: H01L21/58 ,  H01L23/58 ,  G06F17/50

CPC classification number: H01L23/58 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.

公开(公告)号：US20210167013A1

公开(公告)日：2021-06-03

申请号：US17175640

申请日：2021-02-13

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk

IPC: H01L23/528 ,  H01L23/50 ,  H01L21/66 ,  H01L21/768 ,  G06F30/398 ,  H01L25/00 ,  G06F30/394 ,  G06F119/06 ,  H01L21/60

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

公开(公告)号：US10923425B2

公开(公告)日：2021-02-16

申请号：US15873874

申请日：2018-01-17

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk

IPC: H01L23/528 ,  G06F30/394 ,  H01L21/768 ,  G06F30/398 ,  H01L23/50 ,  H01L21/66 ,  H01L25/00 ,  H01L21/60 ,  G06F119/06

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

公开(公告)号：US20180211914A1

公开(公告)日：2018-07-26

申请号：US15873874

申请日：2018-01-17

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk

IPC: H01L23/528 ,  H01L23/50 ,  H01L25/00 ,  H01L21/66

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

公开(公告)号：US09892220B2

公开(公告)日：2018-02-13

申请号：US15456634

申请日：2017-03-13

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Lena Ahlen ,  James Dennis Dodrill

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.