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    Cell architecture with backside power rails
    1.
    发明授权
    Cell architecture with backside power rails 有权

    公开(公告)号：US12248743B2

    公开(公告)日：2025-03-11

    申请号：US17685166

    申请日：2022-03-02

    Applicant: Arm Limited

    Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, Jr.

    IPC: G06F30/398 ,  G06F30/327 ,  G06F30/373 ,  G06F30/394

    Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

    Power grid healing techniques
    3.
    发明授权
    Power grid healing techniques 有权

    公开(公告)号：US10417371B2

    公开(公告)日：2019-09-17

    申请号：US15418602

    申请日：2017-01-27

    Applicant: ARM Limited

    Inventor： Karen Lee Delk ,  Marlin Wayne Frederick, Jr. ,  Ravindra Narayana Rao

    IPC: G06F17/50

    Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.

    Data and clock signal voltages within an integrated circuit
    4.
    发明授权
    Data and clock signal voltages within an integrated circuit 有权
    集成电路内的数据和时钟信号电压

    公开(公告)号：US09450571B2

    公开(公告)日：2016-09-20

    申请号：US14294593

    申请日：2014-06-03

    Applicant: ARM LIMITED

    Inventor： Marlin Wayne Frederick, Jr. ,  Ashwani Kumar Srivastava

    IPC: H03K5/02

    CPC classification number: H03K5/02

    Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

    Abstract translation: 集成电路2具有处理沿着数据通路14通过的数据信号的数据处理电路。耦合到数据处理电路的时钟电路用于调节数据信号沿数据路径的通过。 数据信号以数据信号电压幅度提供，并且以不同的时钟信号电压幅度提供时钟信号。 时钟信号电压幅度高于数据信号电压幅度。 除了数据电源网格10之外还提供了单独的时钟信号电源网格12。

    Method and apparatus for adjusting a timing derate for static timing analysis
    6.
    发明授权
    Method and apparatus for adjusting a timing derate for static timing analysis 有权

    公开(公告)号：US09892220B2

    公开(公告)日：2018-02-13

    申请号：US15456634

    申请日：2017-03-13

    Applicant: ARM Limited

    Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Lena Ahlen ,  James Dennis Dodrill

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

    Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance
    7.
    发明授权
    Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance 有权
    生成包括标准单元和至少一个存储器实例的集成电路布局的方法

    公开(公告)号：US08645893B1

    公开(公告)日：2014-02-04

    申请号：US13658072

    申请日：2012-10-23

    Applicant: ARM Limited

    Inventor： Gus Yeung ,  Martin Jay Kinkade ,  Marlin Wayne Frederick, Jr.

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5068

    Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

    Abstract translation: 公开了一种生成集成电路的布局的方法，该布局包括标准单元和由存储器编译器生成的至少一个存储器实例，以定义集成电路的存储器件。 接收指定所需存储器实例的一个或多个属性的输入数据。 内存编译器基于输入数据并使用指定的内存架构生成所需的内存实例。 提供了一个标准的细胞库。 内存编译器引用标准单元库的至少一个属性，以便生成所需的内存实例。 然后通过用从标准单元库中选择的标准单元格填充标准单元行来生成布局，以便提供集成电路所需的功能组件，并将由存储器编译器提供的所需存储器实例集成到布局中。

    Power rail stitching technique
    9.
    发明授权
    Power rail stitching technique 有权

    公开(公告)号：US11152139B2

    公开(公告)日：2021-10-19

    申请号：US16036673

    申请日：2018-07-16

    Applicant: Arm Limited

    Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Sharrone Rena Smith

    IPC: H01B13/00 ,  H02B3/00 ,  G06F30/392 ,  H01L27/02 ,  G06F119/06 ,  H01L27/118

    Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.

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