公开(公告)号：US10817369B2

公开(公告)日：2020-10-27

申请号：US16225523

申请日：2018-12-19

Applicant: ARM Limited

Inventor： Reiley Jeyapaul ,  Balaji Venu ,  Xabier Iturbe ,  Emre Özer ,  Antony John Penton

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

公开(公告)号：US10289332B2

公开(公告)日：2019-05-14

申请号：US15493609

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Xabier Iturbe ,  Emre Özer ,  Balaji Venu ,  Antony John Penton

IPC: G06F3/06 ,  G06F11/10

Abstract: An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.