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公开(公告)号：US20250036485A1
公开(公告)日：2025-01-30
申请号：US18782668
申请日：2024-07-24
Applicant: Arm Limited
Inventor： Balaji Venu , Metin Gokhan Ünal , Giacomo Gabrielli , Damian Piotr Modrzyk , Dino Santoro
IPC: G06F9/52
Abstract: Provided is a data stream processor comprising: a configurable compute unit comprising plural processing units each configured to receive at least one portion of input data and process the at least one portion of a repetitive arithmetical/logical operation on the data; an input memory unit in electronic communication with the configurable compute unit and configured to supply at least one portion of the input data to at least one of the plural processing units in the configurable compute unit; and at least one accumulator unit in electronic communication with the configurable compute unit and configured to receive at least two portions of processed data from the configurable compute unit and to output accumulated data; wherein each of the plural processing units is further configured to forward its processed data to a next processing unit and/or to an accumulator unit.
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公开(公告)号：US11977896B2
公开(公告)日：2024-05-07
申请号：US17942554
申请日：2022-09-12
Applicant: Arm Limited
Inventor： Matthew James Walker , Mbou Eyole , Giacomo Gabrielli , Balaji Venu , Wei Wang
CPC classification number: G06F9/3856 , G06F9/30145 , G06F9/32 , G06F9/3836 , G06F9/3853 , G06F15/825
Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.
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公开(公告)号：US20200218625A1
公开(公告)日：2020-07-09
申请号：US16823180
申请日：2020-03-18
Applicant: Arm Limited
Inventor： Emre Ozer , Xabier Iturbe , Balaji Venu
Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.
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公开(公告)号：US20240220269A1
公开(公告)日：2024-07-04
申请号：US18261966
申请日：2022-01-19
Applicant: Arm Limited
Inventor： Mbou Eyole , Giacomo Gabrielli , Balaji Venu
IPC: G06F9/38
CPC classification number: G06F9/3853
Abstract: Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.
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5.发明授权公开(公告)号：US10657010B2
公开(公告)日：2020-05-19
申请号：US15800145
申请日：2017-11-01
Applicant: ARM Limited
Inventor： Xabier Iturbe , Emre Ozer , Balaji Venu
Abstract: An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.
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Patent Agency Ranking
公开(公告)号：US10331531B2
公开(公告)日：2019-06-25
申请号：US15447673
申请日：2017-03-02
Applicant: ARM Limited
Inventor： Balaji Venu , Kauser Yakub Johar , Marco Bonino
IPC: G06F11/07 , G06F11/22 , G06F11/24 , G06F11/27 , G06F11/273
Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.
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公开(公告)号：US10303566B2
公开(公告)日：2019-05-28
申请号：US15645053
申请日：2017-07-10
Applicant: ARM LIMITED
Inventor： Emre Özer , Balaji Venu , Xabier Iturbe , Antony John Penton
Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.
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公开(公告)号：US12260221B2
公开(公告)日：2025-03-25
申请号：US18261966
申请日：2022-01-19
Applicant: Arm Limited
Inventor： Mbou Eyole , Giacomo Gabrielli , Balaji Venu
IPC: G06F9/38
Abstract: Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.
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公开(公告)号：US20250037227A1
公开(公告)日：2025-01-30
申请号：US18777526
申请日：2024-07-18
Applicant: Arm Limited
Inventor： Damian Piotr Modrzyk , Metin Gokhan Ünal , Giacomo Gabrielli , Balaji Venu
Abstract: Provided is a graphics processing unit comprising a texture unit, an execution unit, and a machine-learning neural network engine, all configured in a pipeline in electronic communication with an integrated cache memory; and a visual data processing engine comprising a configurable stencil processor integrated into the pipeline, in electronic communication with the integrated cache memory, and configured to execute repetitive image-to-image processing instructions on visual data fetched from the integrated cache memory; wherein a graphics processing unit scheduler is configured to provide a job control function for the visual data processing engine; and wherein the visual data processing engine is configured responsively to the graphics processing unit scheduler to operate in parallel with at least one of the texture unit, the execution unit, or the machine-learning neural network engine using a separate dataflow.
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公开(公告)号：US11966739B2
公开(公告)日：2024-04-23
申请号：US17941387
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James Walker , Mbou Eyole , Giacomo Gabrielli , Balaji Venu
CPC classification number: G06F9/30123 , G06F9/30138 , G06F9/3824 , G06F9/4881 , G06F9/30098 , G06F9/30145
Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
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