公开(公告)号：US11934272B2

公开(公告)日：2024-03-19

申请号：US17742875

申请日：2022-05-12

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard ,  Kar-Lik Kasim Wong

IPC: G06F11/14

CPC classification number: G06F11/1407

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

公开(公告)号：US10523186B1

公开(公告)日：2019-12-31

申请号：US16206234

申请日：2018-11-30

Applicant: Arm Limited

Inventor： Balaji Venu ,  Reiley Jeyapaul ,  Xabier Iturbe ,  Matthew James Horsnell ,  David Michael Gilday

IPC: G06F17/50 ,  G06F9/455 ,  H03K3/037 ,  G01R31/3183

Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal. The vulnerable category comprises those of the flops that are absent from the conditional category and whose change in value is affected by one of the flops or a signal and the isolated category comprises the flops that are absent from the conditional category and that are absent from the vulnerable category.

公开(公告)号：US10909045B2

公开(公告)日：2021-02-02

申请号：US16228042

申请日：2018-12-20

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Reiley Jeyapaul ,  Roxana Rusitoru

IPC: G06F12/14 ,  G06F12/10

Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.

公开(公告)号：US10884850B2

公开(公告)日：2021-01-05

申请号：US16043975

申请日：2018-07-24

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G06F11/20 ,  G06F12/02 ,  G11C29/00

Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.

公开(公告)号：US11022649B2

公开(公告)日：2021-06-01

申请号：US16512911

申请日：2019-07-16

Applicant: Arm Limited

Inventor： Balaji Venu ,  Reiley Jeyapaul

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/30 ,  G01R31/00 ,  G01R31/317 ,  G06F11/00

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

公开(公告)号：US10817369B2

公开(公告)日：2020-10-27

申请号：US16225523

申请日：2018-12-19

Applicant: ARM Limited

Inventor： Reiley Jeyapaul ,  Balaji Venu ,  Xabier Iturbe ,  Emre Özer ,  Antony John Penton

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

公开(公告)号：US10747601B2

公开(公告)日：2020-08-18

申请号：US16206189

申请日：2018-11-30

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Balaji Venu

IPC: G06F17/50 ,  G06F11/00 ,  G06F30/30 ,  G06F30/33 ,  G06F30/367

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.