公开(公告)号：US20220206817A1

公开(公告)日：2022-06-30

申请号：US17137140

申请日：2020-12-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JAGADISH B. KOTRA ,  JOHN KALAMATIANOS

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/52

Abstract: Preserving memory ordering between offloaded instructions and non-offloaded instructions is disclosed. An offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction. In response to completing a cache operation targeting the memory address, the lock on the memory address is removed. For multithreaded applications, upon determining that a plurality of processor cores have each begun executing a sequence of offload instructions, the execution of non-offload instructions that are younger than any of the offload instructions is restricted. In response to determining that each processor core has completed executing its sequence of offload instructions, the restriction is removed. The remote device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US20220188117A1

公开(公告)日：2022-06-16

申请号：US17123270

申请日：2020-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHN KALAMATIANOS ,  MICHAEL T. CLARK ,  MARIUS EVERS ,  WILLIAM L. WALKER ,  PAUL MOYER ,  JAY FLEISCHMAN ,  JAGADISH B. KOTRA

IPC: G06F9/30 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US20210320672A1

公开(公告)日：2021-10-14

申请号：US17348202

申请日：2021-06-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GREG SADOWSKI ,  JOHN KALAMATIANOS

IPC: H03M7/30 ,  H04B1/16 ,  H04B1/04 ,  H04B3/54 ,  H03M5/04

Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.

公开(公告)号：US20210263740A1

公开(公告)日：2021-08-26

申请号：US17238844

申请日：2021-04-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHN KALAMATIANOS ,  KRISHNAN V. RAMANI ,  SUSUMU MASHIMO

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.