公开(公告)号：US12117939B2

公开(公告)日：2024-10-15

申请号：US17557475

申请日：2021-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Saurabh Sharma ,  Jeremy Lukacs ,  Hashem Hashemi ,  Gianpaolo Tommasi ,  Christopher J. Brennan

IPC: G06F12/00 ,  G06F12/0893

CPC classification number: G06F12/0893 ,  G06F2212/6042

Abstract: A processing system selectively allocates storage at a local cache of a parallel processing unit for cache lines of a repeating pattern of data that exceeds the storage capacity of the cache. The processing system identifies repeating patterns of data having cache lines that have a reuse distance that exceeds the storage capacity of the cache. A cache controller allocates storage for only a subset of cache lines of the repeating pattern of data at the cache and excludes the remainder of cache lines of the repeating pattern of data from the cache. By restricting the cache to store only a subset of cache lines of the repeating pattern of data, the cache controller increases the hit rate at the cache for the subset of cache lines.

公开(公告)号：US20230195509A1

公开(公告)日：2023-06-22

申请号：US17557927

申请日：2021-12-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Saurabh Sharma ,  Jeremy Lukacs ,  Hashem Hashemi ,  Gianpaolo Tommasi ,  Guennadi Riguer ,  Mark Fowler ,  Randy Ramsey

IPC: G06F9/48

CPC classification number: G06F9/4831

Abstract: A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.